Thin Film Transistor Array Panel Horizontal Connection Member
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Solution Overview
Problem
In liquid crystal displays, the region occupied by the gate conductor blocks light, reducing transmittance, and existing solutions have not effectively minimized this light-blocking area to improve display efficiency.
Innovation Solution
A thin film transistor array panel design where a connection member elongated in the horizontal direction parallel to the gate line connects the common voltage line and common electrode, reducing the vertical width of the light-blocking area and increasing the size of the pixel electrode, thereby enhancing transmittance and aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate conductor region is enlarged to ensure proper electrical connection and device functionality, then the reliability and ease of manufacture are improved, but the light-blocking area increases and transmittance deteriorates
Solution Approach 1:
The connection member is configured to extend primarily in the horizontal direction (parallel to gate lines) rather than vertically, changing the dimensional orientation of the conductive path. This dimensional reorientation allows electrical connection between common voltage lines and common electrodes while minimizing vertical space occupation, thereby reducing the light-blocking area and improving transmittance without compromising electrical connection reliability
Solution Approach 2:
The connection members are selectively positioned only where electrical connection between common voltage lines and common electrodes is required, rather than uniformly distributing conductive material across the entire substrate. This localized placement ensures proper electrical connectivity at specific points while minimizing the overall light-blocking area, thus improving transmittance without sacrificing connection reliability
2Reliability
If the connection member is extended in the vertical direction to connect common voltage lines and common electrodes, then the electrical connection is ensured, but the light-blocking area increases and transmittance decreases
Solution Approach 1:
The connection member is configured to extend primarily in the horizontal direction (parallel to gate lines) rather than vertically, changing the dimensional orientation of the conductive path. This dimensional reorientation allows electrical connection between common voltage lines and common electrodes while minimizing vertical space occupation, thereby reducing the light-blocking area and improving transmittance without compromising electrical connection reliability
3Illumination intensity
If the pixel electrode size is increased to improve aperture ratio and transmittance, then the light-blocking area is reduced, but the complexity of arranging connection members increases
Solution Approach 1:
The connection members are designed with asymmetric dimensions where the horizontal length (parallel to gate lines) is significantly greater than the vertical width. This asymmetric configuration allows the connection members to extend far enough horizontally to connect common voltage lines and common electrodes effectively while maintaining minimal vertical footprint, thus enabling larger pixel electrodes and improved transmittance without excessive arrangement complexity
Solution Approach 2:
The connection structure is segmented into multiple individual connection members, each connecting a specific common voltage line to a corresponding common electrode. This segmentation allows for systematic and organized arrangement across the substrate, making the overall configuration more manageable and less complex compared to a monolithic connection structure, while still enabling effective electrical connections and supporting larger pixel electrode areas
Data Source
AI summary
A thin film transistor array panel includes: a substrate; a gate line and a common voltage line electrically separated from each other and elongated parallel with each other on the substrate; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connection member on the second passivation layer and electrically separated from each other. The connection member is elongated in a horizontal direction parallel with the gate line and connects the common voltage line and the common electrode to each other.