Fin Selector With Gated RRAM For Memory Scalability
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Solution Overview
Problem
Current RRAM technologies face challenges with scalability, poor resistance uniformity, smaller memory margin, and poor performance of back-end-of-line rectifying diode selectors, limiting their ability to achieve high densities and multi-bit capabilities.
Innovation Solution
The method involves forming a fin selector with a gated RRAM structure, which includes forming a bottom electrode layer and a hardmask on a semiconductor substrate, etching to create a fin-like structure, and then depositing dummy gate stacks, spacers, and interlayer dielectric to create cavities for the RRAM layer, which is made of transition metals, improving resistance distribution and memory margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If planar bottom electrode is used, then device area is reduced, but resistance uniformity deteriorates due to increased filament current paths
Solution Approach 1:
The patent segments the bottom electrode from the planar configuration into a vertical plug structure. This segmentation limits the filament current paths to a controlled vertical region, reducing the number of parallel conduction paths and improving resistance uniformity while maintaining compact device area through vertical integration.
Solution Approach 2:
The patent transitions from a two-dimensional planar bottom electrode to a three-dimensional vertical plug structure. This dimensional change confines the filament formation to a vertical pathway, reducing lateral current spread and improving resistance uniformity without increasing device footprint.
2Area of stationary object
If 1D1R RRAM with metal oxide diodes is used, then cell size is reduced to 4F2, but diode performance deteriorates with low forward current and high Vdd requirement
Solution Approach 1:
The patent changes the diode structure from metal oxide to a vertical fin selector with gated RRAM. This parameter change enables better rectifying properties and tunable characteristics while maintaining the compact 4F2 cell size, improving forward current and reducing Vdd requirements through the fin-based selector architecture.
Solution Approach 2:
The patent employs a composite structure combining fin selector with gated RRAM, integrating the selector and memory functions in a unified vertical architecture. This composite approach improves diode performance through better material composition and structural design while maintaining compact cell size.
3Manufacturing precision
If bottom plug electrode is used to limit filament paths, then resistance distribution improves, but scalability deteriorates
Solution Approach 1:
The patent creates a universal fin selector structure that serves multiple functions: it acts as the bottom electrode, provides the selector diode function, and enables scalable fabrication. This multi-functional vertical fin structure improves reset current distribution while maintaining ease of manufacture through standard semiconductor fabrication processes that can be scaled to high densities.
4Productivity
If fin selector with gated RRAM is used, then scalability and multi-bit capability are improved, but device complexity increases
Solution Approach 1:
The patent utilizes vertical dimensionality with the fin selector structure, enabling multi-bit capability through stacked or adjacent fin configurations. This vertical integration improves scalability by reducing lateral footprint while the modular fin architecture manages complexity through repetitive, standardized structural units that can be fabricated using existing semiconductor processes.
Data Source
AI summary
A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.