Semiconductor Trench Formation via Auxiliary Layer Asymmetry
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges in gap-fill processes due to increased aspect ratios within trenches and interference between memory cells, as the narrowing of trench widths and memory cell gaps complicates insulation and increases electrical interference.
Innovation Solution
A method involving a semiconductor substrate with defined gate insulating and conductive patterns, where an auxiliary polymer layer is formed and etched to create trenches with differentiated top and bottom widths, allowing for easier gap-fill and reduced interference by using isotropic and anisotropic etch processes with gases like HBr, Cl2, and O2, and subsequent removal and treatment processes to compensate for etch damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the trench width is narrowed to increase integration density, then the integration density is improved, but the aspect ratio within the trench increases making the gap-fill process more complex
Solution Approach 1:
An auxiliary layer is formed on the semiconductor substrate before etching the trenches. This preliminary action creates a foundation that enables subsequent trench formation with controlled dimensions, allowing the trench top width to be larger than the bottom width while maintaining high integration density
Solution Approach 2:
The trench is designed with asymmetric dimensions where the top width is larger than the bottom width. This asymmetric geometry is achieved through the auxiliary layer formation and etching process, which resolves the gap-fill complexity by creating a tapered structure that facilitates material deposition while maintaining high integration density
2Productivity
If the gap between memory cells is narrowed to increase integration density, then the integration density is improved, but the interference effect between memory cells increases
Solution Approach 1:
The trench with asymmetric dimensions (wider top than bottom) creates better electrical isolation between adjacent memory cells. The wider top portion provides enhanced spacing that reduces interference effects while still achieving high integration density through the overall compact structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method facilitates improved insulation between memory cells by allowing easier filling of trenches with insulating material and reducing electrical interference, enhancing the manufacturing process efficiency and device performance.
Implementation Method 1
The first etch process is preferably performed using an isotropic etch process
Implementation Method 2
The second etch process preferably is performed using an anisotropic etch process
Implementation Method 3
the isotropic etch process preferably is performed using a dry etch process employing a mixed gas of HBr, Cl2, and O2
Implementation Method 4
the auxiliary layer preferably is formed using CH2F2 gas or C5F8 gas
Implementation Method 5
The treatment process preferably is performed under an atmosphere including only O2 gas or a mixed gas of HBr and O2
Data Source
AI summary
A method of forming semiconductor devices includes providing a semiconductor substrate in which gate insulating patterns and first conductive patterns are formed, performing a first etch process to narrow a width of each of the first conductive patterns, forming an auxiliary layer on the first conductive patterns, the gate insulating patterns, and an exposed surface of the semiconductor substrate, and forming trenches by etching the auxiliary layer and the semiconductor substrate between the first conductive patterns.