TFT Panel Structure with Simultaneous Via Hole Etching
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Solution Overview
Problem
Conventional bottom-gate thin film transistors (TFTs) require six or more masks for manufacturing, making the process complex and costly, especially due to the need for multiple mask processes to form via holes for vertical interconnection.
Innovation Solution
A panel structure and manufacturing method for a display device that uses a simplified process with only five masks by forming all via holes simultaneously through a single etching process, reducing complexity and cost, and includes a 2T-1C structure with a first TFT as a switching transistor and a second TFT as a driving transistor, with conductive plugs and connection wires made of the same material as the pixel electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional bottom-gate TFT manufacturing process is used, then via holes for vertical interconnection can be formed, but six or more masks are required making the process complex and costly
Solution Approach 1:
The patent combines multiple via hole formation steps into a single etching process. Specifically, first via holes connecting the first drain electrode to the first conductive layer, and second via holes connecting the second conductive layer to the third conductive layer, are both formed through one etching step using a single mask pattern, thereby reducing the total mask count from six or more to five masks
Solution Approach 2:
The single mask used in the etching process serves multiple functions: it defines both the first via holes and the second via holes simultaneously, and also defines the pixel electrode and connection wire patterns. This multi-functional mask reduces the overall number of masking steps required in the manufacturing process
2Reliability
If multiple mask processes are used to form via holes, then vertical interconnection can be achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the formation of multiple via holes into a single etching process step. By patternning the mask to include openings for both first via holes and second via holes, the process achieves reliable vertical interconnections through fewer process steps, thereby reducing manufacturing cost while maintaining connection reliability
3Ease of manufacture
If simplified five-mask process is used, then manufacturing cost and complexity are reduced, but via hole formation efficiency must be maintained
Solution Approach 1:
The mask is designed in advance with pre-defined patterns that simultaneously define the locations of first via holes, second via holes, pixel electrode, and connection wires. This preliminary patterning allows all these features to be formed in a single etching step, maintaining high productivity while reducing process complexity
Data Source
AI summary
A panel structure includes a transistor including a gate electrode, a source electrode and a drain electrode, a power source line, a pixel electrode, and one or more contact plugs formed of a same material as the pixel electrode and electrically connecting the power source line and the source electrode.