Bit Line Pre-charge Circuit for NAND Flash Peak Current Reduction
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Solution Overview
Problem
Existing programming techniques for non-volatile storage devices, such as NAND flash memory, face challenges in reducing peak current during the pre-charge phase, which can lead to increased energy consumption and the need for larger charge pumps.
Innovation Solution
Applying a pre-charge voltage to both selected and inhibited bit lines during the channel pre-charge phase, followed by reducing the voltage on inhibited bit lines to a program inhibit voltage and selected bit lines to a program enable voltage, while maintaining the pre-charge voltage in inhibited channels and discharging it from selected channels, to reduce peak current and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a pre-charge voltage is applied only to selected bit lines during channel pre-charge, then the programming operation can proceed, but peak current increases and energy consumption rises
Solution Approach 1:
The patent applies pre-charge voltage to both selected and inhibited bit lines before the actual programming operation begins. This preliminary action pre-charges the channels of all NAND strings, reducing the peak current required during the subsequent programming phase when electrons are injected into the charge storage region. The pre-charge phase prepares the system in advance to minimize energy consumption during the critical programming operation.
2Power
If high pre-charge voltage is applied to all bit lines simultaneously, then channel pre-charge is effective, but peak current increases requiring larger charge pumps
Solution Approach 1:
The patent segments the bit lines into two groups: selected bit lines associated with NAND strings to be programmed, and inhibited bit lines associated with NAND strings to be inhibited from programming. By applying pre-charge voltage to both groups simultaneously and then differentially discharging them, the system achieves effective channel pre-charge while controlling peak current requirements. This segmentation allows the use of standard-sized charge pumps rather than requiring oversized devices.
Solution Approach 2:
The patent implements a two-phase periodic action: first, a pre-charge phase where pre-charge voltage is applied to all bit lines to charge the channels; second, a discharge phase where inhibited bit lines are discharged to program inhibit voltage while selected bit lines are discharged to program enable voltage. This periodic switching between charging and discharging phases allows effective pre-charge while controlling peak current and avoiding the need for larger charge pumps.
3Ease of operation
If pre-charge voltage is applied to inhibited bit lines, then peak current is reduced, but additional voltage switching operations are required
Solution Approach 1:
The patent makes the pre-charge voltage application universal by applying it to both selected and inhibited bit lines during the pre-charge phase. This multi-functional approach serves dual purposes: it pre-charges the channels of selected NAND strings for upcoming programming while simultaneously pre-charging the channels of inhibited NAND strings to prevent program disturb. The same pre-charge voltage and timing structure serves both functions, simplifying the overall control logic despite the additional voltage switching operations required.
Data Source
AI summary
Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.