3D NAND Z-Decoder Shared Driver Architecture
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Solution Overview
Problem
Traditional 2D memory arrays face limitations in reducing memory cell size and increasing density, leading to the development of 3D memory structures to enhance memory capacity and reduce costs, but these structures require a large number of string drivers, increasing power consumption and complexity.
Innovation Solution
A vertical decoder structure is implemented in 3D memory devices to reduce the number of string drivers required, while minimizing power consumption and current needs, by coupling control gates across tiers and using Z-axis decoder circuits to selectively drive memory cell strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D memory structures are implemented to increase memory density, then memory capacity is improved, but the number of string drivers increases leading to higher power consumption and complexity
Solution Approach 1:
The patent merges the functionality of multiple string drivers into a single shared string driver by introducing a vertical decoder structure. The vertical decoder selectively couples the shared string driver to different string groups based on decoded address signals, allowing one driver to serve multiple tiers and groups that would otherwise require separate drivers. This combining approach directly reduces the total number of string drivers needed in the 3D memory system.
Solution Approach 2:
The vertical decoder acts as an intermediary component between the address input and the string driver selection. It receives address signals, decodes them to identify the target string group and tier, and then selectively couples the appropriate string group to the shared string driver. This intermediary structure enables complex selection logic without requiring proportionally more string drivers, thus managing the complexity-density tradeoff.
2Quantity of substance
If more string drivers are used to access more memory strings, then memory capacity is improved, but power consumption increases
Solution Approach 1:
Multiple string driver functions are merged into a single shared string driver through the vertical decoder architecture. Instead of having separate drivers for each tier or string group, one shared driver is time-multiplexed across different string groups based on the decoded address. This merging significantly reduces the total number of active drivers and thus the overall power consumption of the memory system.
Solution Approach 2:
The shared string driver operates periodically, being selectively coupled to different string groups at different times based on the address decoding results. This time-multiplexed operation allows a single driver to serve multiple groups sequentially, reducing the number of simultaneously active drivers and thereby lowering power consumption while maintaining full memory capacity access.
3Device complexity
If traditional 2D memory arrays are used to maintain simple structure, then device complexity is reduced, but memory cell size reduction is limited
Solution Approach 1:
The patent transitions from traditional 2D memory array organization to a 3D structure with vertical stacking of multiple tiers. Memory strings are arranged vertically across multiple tiers stacked along the Z-axis, allowing memory capacity to increase by utilizing the third dimension rather than expanding horizontally. This dimensional change enables continued scaling of memory density without proportionally increasing planar area.
Solution Approach 2:
The 3D memory structure is segmented into multiple tiers and string groups, with each tier containing multiple strings. The vertical decoder further segments the selection process by independently decoding tier addresses and string group addresses. This segmentation allows systematic organization of the 3D space into manageable units that can be selectively accessed, maintaining structural regularity despite the increased dimensionality.
4Use of energy by moving object
If the number of string drivers is reduced to decrease power consumption, then energy efficiency is improved, but the ability to access all memory strings is compromised
Solution Approach 1:
The vertical decoder serves as an intermediary that preserves full memory string accessibility despite using fewer string drivers. It receives complete address information, decodes both tier and string group components, and dynamically couples the appropriate string group to the shared string driver. This intermediary ensures that all strings remain accessible through selective coupling, maintaining full adaptability while reducing driver count.
Solution Approach 2:
The coupling between the shared string driver and string groups is dynamic rather than fixed. The vertical decoder continuously monitors address inputs and dynamically reconfigures which string group is coupled to the driver based on the current access request. This dynamic selection capability ensures that all memory strings remain accessible despite the reduced number of permanent driver connections.
Data Source
AI summary
Apparatus and methods are disclosed, including an apparatus having first and second units of vertically arranged strings of memory cells, each unit including multiple tiers of a semiconductor material, including multiple tiers of memory cells, each tier of memory cells including an access line of at least one memory cell. The access line of a first tier of the first unit can be selectively coupled to a first drive transistor through a first decoder transistor, the access line of a first tier of the second unit can be selectively coupled to the first drive transistor through a second decoder transistor, and the access line of the first tier of the first unit can be selectively coupled to the access line of the first tier of the second unit through the first and second decoder transistors.