3D Semiconductor Device Pass Transistor Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of two-dimensional (2D) semiconductor devices is limited by high costs associated with ultra-high-cost devices needed for finer pattern miniaturization, while three-dimensional (3D) semiconductor devices offer a solution by arranging memory cells in a 3D structure, but face challenges in reducing the number of pass transistors with increasing stacks, which affects high-speed performance.
Innovation Solution
A semiconductor device with multiple substrate layers, where pass transistors are distributed across these layers, reducing their overall number and size, allowing for improved high-speed performance without increasing the size of the row decoder region, even with an increasing number of stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a three-dimensional structure to increase integration degree, then the integration degree is improved, but the number of pass transistors increases with increasing stacks
Solution Approach 1:
The pass transistor groups are segmented and distributed across multiple substrate layers. Each substrate layer contains a subset of pass transistor groups, dividing the total number of pass transistors into manageable segments located in different spatial zones, thereby reducing the concentration and overall impact of pass transistor complexity in any single region.
Solution Approach 2:
The patent transitions from a two-dimensional arrangement where all pass transistors would be located in a single plane to a three-dimensional distribution across multiple stacked substrate layers. This dimensional change allows pass transistors to be spatially separated vertically, reducing the row decoder region size and improving high-speed performance while maintaining the increased integration degree provided by the 3D memory cell structure.
2Quantity of substance
If more pass transistors are used to support increasing stacks, then the memory capacity is improved, but the high-speed performance deteriorates
Solution Approach 1:
Pass transistor groups are segmented and assigned to different substrate layers, reducing the number of pass transistors that must operate within a single timing cycle in any one location. This segmentation allows for better distribution of operational load and reduced signal propagation delays, improving high-speed performance while maintaining increased memory capacity through the distributed architecture.
Solution Approach 2:
By distributing pass transistors across multiple substrate layers in the vertical dimension, the patent reduces the horizontal footprint of the row decoder region. This dimensional redistribution shortens signal paths and reduces interference between pass transistors, thereby improving high-speed performance even as memory capacity increases with additional stacks.
3Device complexity
If pass transistors are concentrated in one region, then the circuit design is simplified, but the device size increases
Solution Approach 1:
The pass transistor groups are segmented and distributed across multiple substrate layers, with each layer containing a portion of the total pass transistor groups. This segmentation allows the row decoder region to be divided into smaller, more manageable sections located in different vertical zones, reducing the overall area required for the row decoder while maintaining circuit functionality through the distributed arrangement.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking multiple substrate layers, each containing distributed pass transistor groups. This dimensional change transforms the row decoder from a large two-dimensional region into a more compact three-dimensional structure, reducing the horizontal footprint and overall device area while maintaining circuit design simplicity through standardized layer configurations.
Data Source
AI summary
A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first substrate layer including a logic circuit, and a plurality of second substrate layers stacked on the first substrate layer, the plurality of second substrate layers including a memory cell array. Each of the plurality of second substrate layers includes, a transfer circuit, coupled to a row line of the memory cell array, that is disposed over the second substrate layer and selectively coupled to a global row line.