Non-volatile Memory Structure with Isolated Charge Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face issues with the second bit effect and program disturbance due to miniaturization, leading to reduced performance and reliability, as the reduced channel length and spacing between elements cause interference during reading and programming operations.
Innovation Solution
A non-volatile memory structure is designed with a substrate, stacked charge storage structures, conductive type doped regions, and a second conductive type doped region with an overlap region, where the charge storage structures are separated and the programmed charge distribution is restricted within the overlap region, reducing interference and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory is miniaturized to increase storage capacity, then the storage density is improved, but the channel length is reduced which makes the second bit effect more obvious and reduces memory performance
Solution Approach 1:
The patent divides the channel region into multiple independent segments by introducing isolation structures (such as oxide layers or doped regions) between adjacent memory cells. This segmentation prevents the electrical interference that causes the second bit effect, allowing each cell to be independently controlled even at reduced dimensions, thus maintaining memory performance while enabling miniaturization for increased storage capacity.
Solution Approach 2:
The patent applies different material properties or doping concentrations in specific local regions of the memory structure. For example, isolation structures are introduced only in critical regions where the second bit effect occurs, while other regions maintain their original characteristics for optimal charge storage. This localized modification eliminates interference without compromising overall device performance, enabling reliable miniaturized memory operation.
2Area of stationary object
If the spacing between elements is shortened to reduce memory size, then the device area is reduced, but program disturbance easily occurs and impairs reliability
Solution Approach 1:
The patent introduces intermediary isolation structures (such as oxide layers or doped regions) positioned between adjacent memory elements. These intermediary structures act as electrical barriers that prevent program disturbance from propagating to neighboring cells, even when the spacing between elements is significantly reduced. This allows the memory device to be miniaturized while maintaining reliability by blocking interference through the intermediary isolation layers.
3Quantity of substance
If a single charge trapping layer is used to store 2 bits per cell, then the storage density is improved, but the second bit effect occurs where reading one bit is affected by the other bit
Solution Approach 1:
The patent physically segments the charge storage region into two independent sections by introducing isolation structures (oxide layers or doped regions) that divide the single charge trapping layer into separate zones. Each zone corresponds to one bit position and is electrically isolated from the other. This segmentation enables 2 bits per cell storage while preventing the second bit effect, as each bit can be read independently without interference from the other bit in the same cell.
Data Source
AI summary
A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.