Thinned Substrate Attachment for Semiconductor Memory Ion Diffusion Control
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Solution Overview
Problem
The challenge in manufacturing semiconductor devices with a MONOS-type stack memory cell is the thermal diffusion of impurity ions from the first semiconductor substrate during high-temperature thermal treatment, which affects the crystalline structure of the dielectric layer and deteriorates the operational characteristics of the device.
Innovation Solution
A method involving the formation of a thinned second semiconductor substrate with a reduced thickness, allowing for thermal treatment without ion diffusion, and the use of plugs to electrically connect selection transistors across substrates, ensuring the dielectric layer is densified and the channel region is formed effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-temperature thermal treatment is performed to densify the dielectric layer, then the crystalline structure of the dielectric layer is improved, but impurity ions thermally diffuse in the first semiconductor substrate, deteriorating operational characteristics
Solution Approach 1:
The patent divides the semiconductor substrate into two separate substrates (first and second substrates) that are processed independently and then attached. This segmentation allows the first substrate to undergo high-temperature thermal treatment for dielectric layer densification without affecting the impurity ion distribution in the second substrate, thereby resolving the contradiction between achieving good crystalline structure and maintaining operational characteristics.
2Reliability
If thermal treatment is performed at low temperature to prevent ion diffusion, then impurity ion distribution is maintained, but the crystalline structure of the dielectric layer becomes sparse, reducing memory cell reliability
Solution Approach 1:
By segmenting the device into two separately processed substrates, the patent enables low-temperature processing of the second substrate to preserve impurity ion distribution, while the first substrate can be independently subjected to high-temperature treatment to achieve proper dielectric layer crystallization. The final attachment combines both benefits.
3Productivity
If two semiconductor substrates are vertically attached to form stack-type memory device, then device integration is achieved, but thermal treatment becomes difficult due to thermal diffusion affecting the first substrate
Solution Approach 1:
The patent maintains the segmented structure of two attached substrates throughout the manufacturing process, performing thermal treatment on the first substrate after attachment but before forming the gate electrode structure on the second substrate. This timing strategy allows thermal treatment to benefit the dielectric layer without causing harmful ion diffusion, as the second substrate with its sensitive impurity regions is already in place and protected.
Solution Approach 2:
The patent performs preliminary actions of forming memory cells on both substrates and attaching them before performing the thermal treatment. This preliminary structuring ensures that when thermal treatment occurs, the dielectric layer is properly positioned and the impurity regions are already defined, allowing the thermal process to densify the dielectric without disrupting critical impurity distributions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a semiconductor device with improved reliability and operational characteristics by preventing thermal diffusion of impurity ions and simplifying the manufacturing process through a single plug formation step.
Implementation Method 1
the dielectric layer may be thermally treated at a high temperature of about 900° C. to about 1,100° C.
Implementation Method 2
the impurity ions in the impurity regions of the first semiconductor substrate may thermally diffuse when temperatures are in the high temperature range
Implementation Method 3
The flash memory device may be classified as a floating gate-type non-volatile memory device, a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile memory device, or a metal-oxide-nitride-oxide-silicon (MONOS)-type non-volatile memory device... electrically controls input/output of data using Fowler-Nordheim (F-N) tunneling
Data Source
AI summary
In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.