Semiconductor Memory Device 3D Bit Line Segmentation
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Solution Overview
Problem
The increasing integration of semiconductor memory devices poses challenges in reducing circuit area and manufacturing costs while maintaining effective data storage and retrieval, particularly in three-dimensional configurations where voltage control and current supply are critical.
Innovation Solution
The semiconductor memory device incorporates a configuration with transistors TFT1 and TFT2 in the same layer, connected to global and local bit lines, and variable resistance films, allowing for reduced circuit area and common manufacturing processes, enabling easier voltage control and increased current supply through parallel semiconductor sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to increase integration, then storage capacity is improved, but voltage control and current supply become more difficult
Solution Approach 1:
The bit line is divided into a global bit line and multiple local bit lines. Each local bit line is independently controllable and connects to specific memory cell strings, enabling selective voltage application to particular regions of the three-dimensional memory structure. This segmentation allows efficient voltage control and current supply across the integrated memory array without requiring complex global voltage distribution.
2Quantity of substance
If integration level is increased, then storage capacity is improved, but circuit area and manufacturing costs increase
Solution Approach 1:
Memory cells are arranged in a three-dimensional configuration with memory cell strings extending in the vertical direction above the substrate. Multiple local bit lines are disposed at different heights (first local bit line above second local bit line), utilizing the vertical dimension for routing. This three-dimensional arrangement increases storage capacity while maintaining efficient use of planar circuit area.
3Quantity of substance
If more wirings are added for three-dimensional configuration, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The global bit line serves multiple functions: it acts as a common electrical connection for multiple local bit lines, provides a reference potential, and enables selective activation of different memory regions through voltage application. This multi-functional design reduces the need for additional dedicated wirings, simplifying the manufacturing process while maintaining three-dimensional memory functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces circuit area, lowers manufacturing costs, and facilitates efficient data storage and retrieval with reduced voltage requirements, enhancing the performance and efficiency of the semiconductor memory device.
Implementation Method 1
a variable resistance film provided between the first wiring and the second wiring
Data Source
AI summary
A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.