Memory Device Refresh Circuit for Multilevel Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in maintaining multilevel data retention characteristics due to charge transfer, which affects the accuracy and longevity of stored data.
Innovation Solution
A memory device comprising a memory cell and a refresh circuit with a compensation voltage generator circuit, a voltage adder circuit, and a refresh timing control circuit, where the memory cell uses a combination of oxide semiconductor and silicon transistors to retain multiple potentials by adjusting charge transfer, and the refresh circuit compensates for potential changes to maintain original data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge transfer is used to retain multilevel data in the memory cell, then data storage capacity is improved, but potential changes occur due to charge transfer which deteriorate data retention accuracy
Solution Approach 1:
The refresh circuit reads the potential from the memory cell, compares it with the expected potential, and generates a compensation voltage based on the difference. This compensation voltage is then fed back to correct the potential, forming a closed-loop feedback system that maintains data retention accuracy despite charge transfer effects
Solution Approach 2:
The system dynamically adjusts the compensation voltage parameter based on the actual potential read from the memory cell. By changing the compensation voltage in response to measured potential deviations, the system corrects for charge transfer effects and maintains accurate data retention
2Measurement precision
If refresh operations are performed frequently to maintain data accuracy, then data retention accuracy is improved, but the interval between refresh operations increases which reduces productivity
Solution Approach 1:
The compensation voltage generator dynamically adjusts the compensation voltage parameter based on the actual potential read from the memory cell. By optimizing this parameter, the system achieves accurate data retention with reduced refresh frequency, improving operational efficiency
Solution Approach 2:
The refresh circuit autonomously determines when and how much compensation is needed by reading the memory cell potential and generating appropriate compensation voltages. This self-regulating mechanism optimizes refresh operations without requiring external intervention, balancing accuracy and efficiency
3Device complexity
If a simple memory cell structure is used, then device complexity is reduced, but the ability to retain multilevel data with charge transfer compensation is insufficient
Solution Approach 1:
The refresh circuit serves multiple functions: it reads the memory cell potential, generates compensation voltages, and writes corrected data back to the memory cell. This multi-functional approach enables sophisticated multilevel data retention without requiring separate dedicated circuits for each function
Solution Approach 2:
The compensation voltage generator acts as an intermediary between the memory cell and the refresh operation. It processes the read potential and generates the appropriate compensation voltage that mediates the correction process, enabling reliable multilevel data retention while keeping the overall structure manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively extends the interval between refresh operations, ensures accurate data retention by compensating for potential changes, and maintains multilevel data integrity despite charge transfer, thereby enhancing the memory device's data retention characteristics.
Implementation Method 1
multilevel data be retained by retaining charge between the one of the source and the drain of the first transistor and the gate of the second transistor
Implementation Method 2
the plurality of potentials are changed by charge transfer
Implementation Method 3
supplying the memory cell with a potential obtained by adding a potential read from the memory cell and a potential corresponding to the amount of potential change due to the charge transfer
Data Source
AI summary
Provided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a first transistor, one of a source and a drain of a second transistor, and one of electrodes of a capacitor. The refresh circuit is configured to refresh the memory cells. That is, the refresh circuit is configured to determine an interval between refresh operations, estimate a change of the potential of the node due to the leakage of the charge, and provide a refresh potential to the memory cells, where the refresh potential is a sum of the potential read from the node and the potential lost due to the charge leakage.