3D Vertical Channel Memory Structure for Read and Erase Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current two-dimensional semiconductor devices face limitations in integration due to the area occupied by unit memory cells, and three-dimensional semiconductor memory devices are needed to enhance integration, but they struggle with read and erase characteristics.
Innovation Solution
A semiconductor memory device with a conductive layer, insulating isolation layer, and a stack structure featuring alternating source/drain and gate electrode layers, along with a vertical channel layer connected to the conductive layer, which includes doped regions and gate insulating layers to improve read and erase operations by controlling voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory devices are used to increase integration, then the degree of integration is improved, but read and erase characteristics deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with source/drain contact layers and gate electrode layers alternately arranged. This dimensional change dramatically increases the degree of integration while maintaining controlled electrical characteristics through the vertical channel structure connecting to the conductive layer.
Solution Approach 2:
The patent introduces a conductive layer positioned between the substrate and the vertical channel layer. This conductive layer acts as an intermediary that enables controlled voltage application to the vertical channel, thereby improving read and erase characteristics. The conductive layer mediates the electrical interaction between the substrate and the three-dimensional memory cell structure, resolving the contradiction between high integration and reliable operation.
2Reliability
If voltage is applied to control read and erase operations, then read and erase characteristics are improved, but leakage current increases
Solution Approach 1:
The patent implements localized doping with different conductivity types in specific regions of the vertical channel layer. Source/drain regions are doped with a second conductivity-type impurity while other regions maintain the first conductivity type. This local quality differentiation enables controlled voltage application for improved read and erase operations while minimizing leakage current through strategic placement of conductive regions.
Solution Approach 2:
The patent utilizes changes in electrical conductivity parameters through controlled doping of the vertical channel layer with first and second conductivity-type impurities. By adjusting the concentration and distribution of doped regions, the patent optimizes the balance between achieving reliable read and erase characteristics through voltage control and minimizing leakage current losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances read and erase characteristics by reducing leakage current and increasing erase speed through controlled voltage application, thereby improving the overall performance of three-dimensional semiconductor memory devices.
Implementation Method 1
a vertical channel layer extending through the stack structure and the insulating isolation layer, wherein the vertical channel layer is in contact with each of the plurality of source/drain contact layers, and is connected to the conductive layer
Implementation Method 2
a vertical channel layer extending through the stack structure and the insulating isolation layer, wherein the vertical channel layer is in contact with each of the plurality of source/drain contact layers, and is connected to the conductive layer; source/drain regions of the vertical channel layer that are doped with a second conductivity-type impurity
Data Source
AI summary
A semiconductor memory device is provided. The semiconductor memory device includes: a conductive layer on a substrate; an insulating isolation layer on the conductive layer; a stack structure on the insulating isolation layer, the stack structure including a plurality of source/drain contact layers and a plurality of gate electrode layers alternately provided along a first direction, perpendicular to an upper surface of the substrate; a vertical channel layer extending through the stack structure and the insulating isolation layer, wherein the vertical channel layer is in contact with each of the plurality of source/drain contact layers, and is connected to the conductive layer; and a gate insulating layer between each of the plurality of gate electrode layers and the vertical channel layer.