3D Memory Read Voltage Control for Word Line Coupling Interference

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Solution Overview

Problem

The increasing number of layers in 3D memory devices leads to serious coupling interference between layers, affecting the threshold voltage distribution and reducing the read window margin, thereby impairing the read performance of the memory device.

Innovation Solution

The memory device employs a peripheral circuit to perform read operations with different read voltages based on the type of word lines, applying a first read voltage to one type and a second read voltage to another type, with the second pass voltage adjusted according to adjacent threshold voltage distributions, and applying different pass voltages to unselected word lines to reduce read disturbance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of layers in 3D memory devices is increased to increase storage density, then storage density is improved, but coupling interference between layers worsens, affecting threshold voltage distribution and read window margin

Engineering Contradiction:
Improvestorage densityVSAvoidcoupling interference
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent segments word lines into different types (first type and second type) based on their position and interference characteristics. Memory cells are divided into first memory cells (coupled to first word lines) and second memory cells (coupled to second word lines). This segmentation allows different read operations to be applied to different segments, addressing the coupling interference problem by treating affected and unaffected regions differently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different read operations locally to different memory cell groups. First read operation is applied to first memory cells (not affected by coupling interference), while second read operation with adjusted pass voltage is applied to second memory cells (affected by coupling interference). This local quality approach optimizes read performance for each specific region based on its interference characteristics.

Inventive Principle:
Principle #3Local quality

2Reliability

If different read operations are applied to memory cells coupled to different types of word lines to reduce read disturbance, then read performance is improved, but device complexity increases

Engineering Contradiction:
Improveread performanceVSAvoidoperational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary classification of word lines into first type and second type based on their position in the memory device. This preliminary action is done during programming or initialization, so that during read operations, the controller can quickly determine which read operation to apply without complex real-time analysis. The pass voltage adjustment for the second read operation is also predetermined based on threshold voltage distribution characteristics.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback from threshold voltage distribution analysis to adjust the pass voltage in the second read operation. The controller analyzes the threshold voltage distribution of memory cells and adjusts the pass voltage accordingly to compensate for coupling interference effects. This feedback mechanism optimizes read performance while maintaining manageable complexity through automated adjustment.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12548627B2Memory devices and operating methods thereof, and memory systems
Publication Date: 2026.02.10 YANGTZE MEMORY TECH CO LTD
  • US12548627B2 patent drawing
  • US12548627B2 patent drawing
  • US12548627B2 patent drawing

AI summary

A memory device includes: a memory array; the memory array includes memory cells and word lines coupled to the memory cells; and a peripheral circuit coupled to the memory array and configured to: perform a first read operation, wherein the first read operation includes: applying a first read voltage to a first word line of the word lines that belongs to the first type; and applying a first pass voltage to word lines except the first word line; perform a second read operation, wherein the second read operation includes: applying a second read voltage to a second word line of the word lines that belongs to the second type; applying a second pass voltage to word lines which are adjacent to the second word line; and applying the first pass voltage to word lines except both of the second word line and the word lines adjacent to the second word line.