3D Semiconductor Memory Device with Recrystallized Active Pillars
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited by the high cost and complexity of forming micro patterns, making it challenging to achieve both low manufacturing costs and reliable production for three-dimensional semiconductor memory devices with improved electrical characteristics.
Innovation Solution
A three-dimensional semiconductor memory device with a stacked structure featuring conductive patterns, active pillars, and data storage patterns, where the active pillar includes a vertical semiconductor pattern and protruding semiconductor patterns with a different crystalline structure, and the data storage patterns are separated and contacted by insulation and conductive layers, allowing for improved electrical characteristics and manufacturing methods involving laser recrystallization and deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory device is used, then manufacturing cost is reduced, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, with conductive patterns and active pillars arranged in three dimensions. This dimensional change enables significantly higher integration density without requiring more complex micro pattern formation processes, as the stacking can be achieved through sequential deposition and etching steps rather than advanced lithography.
2Quantity of substance
If three-dimensional semiconductor memory device is used, then integration density is improved, but manufacturing cost increases
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete layers including first and second conductive patterns, intermediate insulation layers, and active pillars with different crystalline structures. Each layer can be formed using standard semiconductor fabrication processes, allowing modular manufacturing. The segmentation enables complex 3D architecture to be built through sequential processing steps rather than requiring expensive advanced equipment.
Solution Approach 2:
The patent employs parameter changes in the crystalline structure of semiconductor patterns, creating regions with different crystallinity (amorphous, polycrystalline, single-crystal) to optimize electrical characteristics. By controlling deposition conditions and thermal processing parameters, the device achieves improved performance without requiring expensive specialized equipment, as these parameter changes can be implemented through standard CVD, PVD, and annealing processes.
3Reliability
If uniform semiconductor pattern is used, then manufacturing process is simplified, but electrical characteristics are degraded
Solution Approach 1:
The active pillar structure incorporates different crystalline structures at different locations: amorphous or polycrystalline semiconductor in the lower portion for mechanical stability and ease of formation, and single-crystal or highly-oriented polycrystalline semiconductor in the upper portion for superior electrical characteristics. This local quality differentiation optimizes both manufacturing feasibility and device performance, with each region tailored to its specific functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the integration density and electrical performance of three-dimensional semiconductor memory devices, reducing grain boundaries and improving charge mobility, thus enabling faster data reading and writing while maintaining lower manufacturing costs.
Implementation Method 1
forming first semiconductor patterns by recrystallizing the preliminary semiconductor patterns exposed to the first penetration region
Implementation Method 2
recrystallizing the preliminary semiconductor patterns
Implementation Method 3
forming second semiconductor patterns to contact the first semiconductor patterns and the substrate in the first penetration region
Data Source
AI summary
A three-dimensional semiconductor memory device includes a stacked structure including a plurality of conductive patterns, an active pillar penetrating the stacked structure, and a data storage pattern between the active pillar and the conductive patterns, wherein the active pillar includes a vertical semiconductor pattern penetrating the stacked structure and protruding semiconductor patterns between the vertical semiconductor pattern and the data storage pattern, the protruding semiconductor patterns having a different crystalline structure from that of the vertical semiconductor pattern.