3D Semiconductor Memory Redistribution Lines
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase integration density while minimizing the number of metal layers, as the number of wiring lines and metal layers required increases with the number of stacked row lines, leading to higher manufacturing costs and potential failures.
Innovation Solution
The semiconductor memory device incorporates a redistribution line system in the pad layers of both the memory and circuit chips, allowing for reduced metal layers without decreasing memory block count, by strategically placing redistribution lines in available spaces around contact pads, thus simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of row lines is increased to increase integration density, then the degree of integration is improved, but the number of wiring lines and metal layers increases, leading to higher manufacturing costs and complexity
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture. Multiple row lines are arranged vertically in different layers, allowing integration density to increase without proportionally increasing the number of metal layers. The memory cell array is configured with row lines extending in a first direction and bit lines in a second direction, creating a three-dimensional memory structure that improves integration while controlling wiring complexity.
Solution Approach 2:
The memory device is divided into multiple stacked layers with row lines separated into different levels. Each row line is segmented and positioned at different vertical heights, coupled to bit lines through vertically stacked memory cells. This segmentation allows the wiring to be distributed across layers rather than concentrated in a single plane, reducing the number of metal layers required.
2Quantity of substance
If the number of row lines is increased to increase integration density, then the degree of integration is improved, but manufacturing cost increases due to more wiring lines and metal layers
Solution Approach 1:
By stacking row lines vertically in three dimensions rather than arranging them horizontally in two dimensions, the patent achieves higher integration density without proportionally increasing the number of metal layers. This vertical stacking reduces the total wiring length and metal layer count, thereby lowering manufacturing costs while maintaining high integration.
Solution Approach 2:
The bit lines are configured to extend in a second direction perpendicular to the row lines and are coupled to multiple row lines from different layers. This multi-functional bit line structure serves multiple row lines simultaneously, reducing the total number of wiring lines required and simplifying the manufacturing process.
3Quantity of substance
If the number of row lines is increased to increase integration density, then the degree of integration is improved, but the number of wiring lines increases, leading to more metal layers
Solution Approach 1:
The patent employs a three-dimensional architecture where row lines are stacked vertically and bit lines extend perpendicular to them. This spatial arrangement allows multiple row lines to be accessed through a reduced number of bit lines, decreasing the total wiring count while achieving high integration density.
Solution Approach 2:
Multiple row lines from different layers are merged and coupled to common bit lines. The bit lines serve as shared conduits that connect to multiple row lines simultaneously, reducing the total number of individual wiring connections required and simplifying the overall wiring architecture.
Data Source
AI summary
A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.