3D Memory Page Refresh Grouping for Disturb Error Reduction
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Solution Overview
Problem
Existing 3-dimensional memory circuits face issues with data integrity due to programming or erase disturbs in non-selected storage transistors, which are vulnerable to interference from shared bias voltages, leading to undesired programming or erasing.
Innovation Solution
A method is implemented to divide memory pages into refresh groups, perform write operations concurrently with data write-back, and apply predetermined voltage differences to minimize disturbs by using a schedule and redundancy to ensure data integrity, with specific voltage configurations for selected and non-selected transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage transistors share common bit lines and word lines in a 3-dimensional array, then memory density is improved, but non-selected transistors experience programming or erase disturbs from shared bias voltages
Solution Approach 1:
The patent divides memory pages into multiple refresh groups (e.g., Group 1, Group 2, etc.) to segment the data storage structure. This segmentation allows the system to manage and refresh specific groups of pages independently, reducing the impact of disturb operations on non-selected transistors while maintaining high memory density through the 3-dimensional array architecture.
Solution Approach 2:
The patent performs preliminary refresh operations on selected refresh groups before and during programming/erase operations. By proactively refreshing data in specific groups, the system prevents disturb errors from accumulating and corrupting data integrity, thereby resolving the contradiction between high density and reliability.
2Reliability
If a predetermined voltage difference is imposed across word line and common bit line to inhibit disturbs, then non-selected transistor reliability is improved, but the voltage difference magnitude is reduced compared to required programming/erase operations
Solution Approach 1:
The patent applies different voltage configurations to different lines based on their function. Specifically, it maintains a first voltage difference across the selected word line and common bit line for the target transistor, while applying a second (smaller) voltage difference to non-selected lines. This local differentiation allows effective disturb protection without requiring high voltage magnitudes across all lines, resolving the contradiction between protection effectiveness and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces program and erase disturbs in non-selected storage transistors, maintaining data integrity by limiting the number of disturbs within each refresh group and ensuring data redundancy.
Implementation Method 1
Data is stored in a charge-trapping layer (e.g., a silicon oxide-silicon nitride-silicon oxide triple layer) in each storage transistor
Data Source
AI summary
A method is for ensuring data integrity in memory pages includes: dividing the memory pages into a predetermined number of refresh groups; and for each write operation to be performed on a selected memory page: (a) selecting one of the refresh groups; (b) reading data from the memory pages of the selected refresh group; and (d) concurrently (i) performing the write operation on the selected memory page, and (ii) writing back the data read into the memory pages of the selected refresh group.