3D Memory Block Layout With Ring Channels for Higher Density
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Solution Overview
Problem
Two-dimensional memory arrays have reached scaling limits, hindering further improvements in memory density.
Innovation Solution
A memory block design featuring stacked strip structures with alternately arranged insulating and conductive strips, and semiconductor structures forming memory subarrays, where conductive strips act as control gates for memory-cell groups, enabling efficient memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory array is used, then manufacturing process is simple, but memory density cannot be further improved
Solution Approach 1:
The patent transitions from a two-dimensional memory array to a three-dimensional stacked structure. Multiple memory layers are stacked vertically along the third dimension, with each layer containing memory cells formed by alternating insulating and conductive strips. This vertical stacking enables significant increase in memory density without proportionally increasing the footprint area, directly resolving the contradiction between memory density and structural complexity.
Solution Approach 2:
The patent implements a nested structure where memory layers are stacked within a vertical column space. Each memory layer contains conductive strips and insulating strips that are nested alternately, with semiconductor structures positioned between adjacent stacked structures. This nesting approach maximizes the use of vertical space to achieve higher memory density while maintaining a compact overall structure.
2Quantity of substance
If stacked strip structures are implemented, then memory density is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory structure into multiple discrete stacked layers, with each layer containing segmented conductive strips and insulating strips. The memory array is partitioned into multiple memory layers stacked vertically, with each layer independently formed but collectively contributing to the overall memory density. This segmentation allows for modular manufacturing and simplifies the complexity management of the three-dimensional structure.
Solution Approach 2:
The stacked strip structures serve multiple functions simultaneously: they form memory cells, provide electrical connections through conductive strips, offer insulation through insulating strips, and enable vertical stacking for increased density. The semiconductor structures between adjacent stacked structures also serve dual purposes as both structural elements and functional components of the memory cells, reducing overall device complexity despite the three-dimensional architecture.
Data Source
AI summary
The memory block includes a memory array including stacked strip structures spaced apart from each other along a column direction and semiconductor structures. Each stacked strip structure extends along a row direction, and includes insulating strips and conductive strips alternately stacked along a height direction. Some of the semiconductor structures are arranged between every two adjacent stacked strip structures. Every two adjacent stacked strip structures and the semiconductor structures arranged therebetween are involved in forming a row of memory subarray. The conductive strips in the two adjacent stacked strip structures serve as control gates of the row of memory subarray. The row of memory subarray includes memory-cell groups distributed along the row direction. Each memory-cell group includes a corresponding semiconductor structure that extends along the height direction. On a plane perpendicular to the height direction, the cross section of the semiconductor structure is ring-shaped.