3D Memory Cell Layout With ROM Contact Plug Integration
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Solution Overview
Problem
The challenge of improving the degree of integration and operational reliability of semiconductor devices, particularly in three-dimensional structures, is limited by the area occupied by unit memory cells and the complexity of manufacturing processes.
Innovation Solution
A semiconductor device is designed with a source structure, gate structure, and channel structure, incorporating a read-only memory area with contact plugs that extend through stacks and sacrificial layers, allowing for a stable three-dimensional arrangement of memory cells and efficient integration of read-only memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stacking structure is implemented to improve integration density, then the area occupied by unit memory cells is reduced, but the operational reliability becomes difficult to ensure
Solution Approach 1:
The source structure is divided into distinct cell area and edge area, with different structural configurations in each region. The cell area contains the main memory cells while the edge area contains the read-only memory area with contact plugs, allowing differentiated functional optimization that maintains reliability while achieving high integration density through vertical stacking.
Solution Approach 2:
Different regions of the semiconductor device are given different structural properties: the cell area has a specific stack and gate structure for memory operations, while the edge area has a read-only memory area with contact plugs extending through stacks. This local differentiation ensures that each region is optimized for its specific function, maintaining operational reliability while achieving high overall integration density.
2Quantity of substance
If multiple stacks are formed to increase storage capacity, then the data storage capability is improved, but the manufacturing process complexity increases
Solution Approach 1:
Sacrificial layers are formed in advance within the stacks before the final memory structures are completed. These sacrificial layers serve as placeholders that guide subsequent manufacturing steps, allowing multiple stacks to be formed systematically with predetermined contact plug positions, thereby increasing storage capacity while managing manufacturing complexity through pre-planned structural guidance.
Solution Approach 2:
Sacrificial layers act as intermediary structures during the manufacturing process. These temporary structures facilitate the formation of contact plugs and define the architecture of multiple stacks without requiring direct complex patterning of the final structures. The sacrificial layers are later removed, having served their purpose of guiding the manufacturing process for high-capacity multi-stack formation.
3Productivity
If contact plugs are extended through multiple stacks to form read-only memory area, then the data retrieval efficiency is improved, but the manufacturing precision requirements become more stringent
Solution Approach 1:
Sacrificial layers serve as intermediary structures that pre-defin e the exact positions and paths where contact plugs need to be formed. By having these sacrificial layers in place before contact plug fabrication, the manufacturing process achieves high precision alignment automatically, as the contact plugs are formed to replace or connect to the pre-positioned sacrificial layers, enabling efficient data retrieval without excessively stringent precision requirements.
Solution Approach 2:
The sacrificial layers are formed in advance at the precise locations where contact plugs will eventually be positioned. This preliminary action establishes the geometric constraints and alignment references needed for subsequent contact plug formation, ensuring that data retrieval efficiency is achieved through properly positioned contact plugs without requiring extremely tight manufacturing tolerances during the actual contact plug fabrication step.
Data Source
AI summary
A semiconductor device includes: a source structure comprising a cell area and an edge area; a stack located on the edge area of the source structure; a gate structure located on the cell area of the source structure; a channel structure connected to the cell area of the source structure by extending through the gate structure; and a read-only memory area.