3D Memory Tile Segmentation to Reduce Capacitance and Leakage
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Solution Overview
Problem
Existing 3D memory technologies face challenges with high bit line capacitance and background leakage current, which hinder operating speed.
Innovation Solution
The 3D memory design includes a structure with tiles divided into sub-tiles, separated local bit lines, and conductive patterns that connect to a global bit line, reducing the number of sectors driven by each bit line transistor and shortening local bit line length to lower capacitance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bit line transistor structure drives more sectors to increase area utilization, then the storage capacity is improved, but the bit line capacitance and background leakage current increase
Solution Approach 1:
The bit line is divided into multiple local bit lines, each driven by separate bit line transistor structures. This segmentation reduces the capacitance and leakage current for each individual bit line while maintaining the overall storage capacity through increased number of bit lines.
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing multiple local bit lines at different heights (first height and second height) above the substrate. This three-dimensional arrangement allows more bit lines to be packed into the same planar area, increasing storage capacity without proportionally increasing the lateral capacitance and leakage current.
2Quantity of substance
If the local bit line length is increased to cover more sectors, then the storage capacity is improved, but the bit line capacitance increases
Solution Approach 1:
Each local bit line is assigned to a specific sector or group of sectors and has a limited, optimized length. Multiple local bit lines are used to cover the entire storage area, rather than having a single long bit line. This segmentation reduces the length of each individual bit line while maintaining total storage capacity.
Solution Approach 2:
The patent utilizes vertical stacking to place bit lines at different heights, allowing the bit line network to extend in the vertical dimension rather than requiring all bit lines to be extremely long in the planar direction. This reduces the effective length of each local bit line while covering more sectors through three-dimensional routing.
Data Source
AI summary
A 3D memory including a plurality of tiles, a bit line transistor structure, a first upper conductive layer, and a second upper conductive layer. The bit line transistor structure is disposed between a first sub-tile and a second sub-tile in the plurality of tiles. The first upper conductive layer includes a plurality of local bit lines, a plurality of local source lines and a conductive pattern. The plurality of local bit lines include a first group and a second group of local bit lines separated from each other, wherein two adjacent local bit lines are disposed between adjacent two local source lines. The second upper conductive layer includes a global bit line. The global bit line is electrically connected to the local bit lines through the conductive pattern. The 3D memory could be a 3D AND flash memory with high capacity and high performance.