3D Memory Devices with Segmented Computing and Storage Regions
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Solution Overview
Problem
Existing 3D memory systems are limited by having only one type of memory, which restricts their multi-functionality in computing-in-memory (CIM) applications, where both high-bandwidth computing and mass data storage are needed, leading to suboptimal performance and area usage.
Innovation Solution
A 3D memory device with two types of memory cells: high-endurance memory cells for computing and 2-bit memory cells for data storage, fabricated on the same chip, sharing source/select lines to reduce area and cost, and enhance performance by placing computing and data storage memories close together.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If only one type of memory is used in 3D memory systems, then the device structure is simple, but the multi-functionality in CIM applications is limited
Solution Approach 1:
The memory device is segmented into two distinct memory regions: a first memory region with first memory cells optimized for high-bandwidth computing operations, and a second memory region with second memory cells optimized for mass data storage. This segmentation allows each region to serve its specific function optimally while maintaining overall system versatility for different CIM applications.
Solution Approach 2:
Different regions of the memory device are assigned different memory cell types with specialized characteristics. The first memory cells have characteristics suited for computing operations (higher speed, lower density), while the second memory cells have characteristics suited for storage (higher density, lower speed). This local differentiation of quality enables the system to handle both computing and storage requirements simultaneously.
2Reliability
If separate memory chips are used for computing and storage, then each memory type can be optimized, but the area and cost increase
Solution Approach 1:
The patent merges both computing-optimized memory cells and storage-optimized memory cells onto a single integrated memory chip. This consolidation eliminates the need for separate memory chips, reducing the overall area footprint and cost while maintaining the performance benefits of having specialized memory regions for both computing and storage functions.
3Loss of time
If memory cells are placed far apart, then routing is simpler, but latency increases
Solution Approach 1:
The patent utilizes three-dimensional vertical stacking to place different memory cell types in close proximity along the vertical dimension rather than requiring horizontal separation. This allows first memory cells and second memory cells to be positioned adjacent to each other in the vertical direction, reducing access latency while the routing complexity is managed through the structured 3D architecture and shared select lines.
Data Source
AI summary
A semiconductor device includes a substrate including, in a first area, a first semiconductor channel coupled to a portion of a first memory layer, and first, second, and third conductive structures. The first and third conductive structures are coupled to end portions of a sidewall of the first semiconductor channel, with the second conductive structure coupled to a middle portion of the sidewall. The semiconductor device includes, in a second area, a second semiconductor channel coupled to a first portion of a second memory layer, and fourth and fifth conductive structures. The fourth and fifth conductive structures are coupled to end portions of a sidewall of the second semiconductor channel, with no vertically extending conductive structure interposed between the fourth and fifth conductive structures.