Read-Only Memories TRIZ Cases

Sequential voltage source sequencing maintains relative biasing between components, preventing voltage inversion and data integrity loss during low-power modes.

A precision tuning algorithm segments programming pulses to store weight values in non-volatile memory cells.

Biasing bit lines with intermediate voltage narrows threshold voltage distributions without reducing overall programming throughput.

A nonvolatile memory device uses segmented program currents to set target resistance distributions in variable resistance cells.

A signal generation circuit adjusts internal output potential levels to stabilize the final output signal.

A regulated sink current source decouples sensing speed from source terminal voltage variations to improve memory read accuracy.

Segmented voltage domains and local conversion mechanisms resolve transistor performance trade-offs while maintaining energy efficiency.

Dynamic precharge voltages optimize the sense window for multi-level memory cells, resolving storage density versus sensing accuracy trade-offs.

Dynamic bit line biasing tightens threshold voltage distributions, preventing state overlap and reading errors in multi-level flash memory cells.

A memory device uses a peripheral circuit to perform second refresh operations on weak memory cells.

A discharge circuit manages voltage transitions in non-volatile memory switching circuits during operation abortion.

Control circuitry repurposes a corrupted select device by programming a nearby data word line to function as a new selection line, preserving data integrity.

A multi-circuit control system shifts status information through serially coupled NAND flash circuits using a read clock signal.

Segmented back gates prevent lateral electron diffusion and unintended programming, maintaining reliability as vertical cell counts increase.

A memory device integrates a counting circuit and control logic to execute data restoring operations independently.

Capacitive detection circuit initializes amplifier to measure leakage current changes, reducing die area while maintaining accuracy.

This programming method reduces threshold voltage distribution errors by simultaneously executing multiple programming cases on different memory cell groups.

Pre-charging sensing nodes in page buffers reduces bit line recovery times, accelerating read operations despite higher storage density.

A page buffer with dual registers and a data I/O unit manages multi-level cell programming in non-volatile memory devices.

Varying rectangular waveform duty cycles on memory control lines reduces voltage generation complexity and power consumption.

A memory controller stores system operating information before background operations to enable rapid roll-back upon detecting internal faults.

Self-boosting inhibits disturb in unselected cells during hot carrier assisted programming, reducing high voltage requirements and manufacturing complexity.

A non-volatile memory device reads data from erased sectors during a multi-sector erase operation.

Bit line control circuit manages clamp transistor connections to sense amplifiers, preventing mutual interference during read operations.

A memory controller pauses write operations using a register to hold data and voltage.

A memory controller dynamically determines minimum resume latency for erase operations based on device conditions.

Applying a preconditioning current stabilizes the threshold voltage of non-volatile memory cells, reducing electron trapping effects that cause read errors.

A nonvolatile memory device synchronizes data transfer with a second clock signal having twice the cycle of a first clock signal.

Alternating odd and even row programming sequences minimize word line coupling, tightening threshold voltage distributions to enhance data reliability.

Segmenting memory arrays by cell density enables independent operation of high-performing portions.

A memory controller switches a flash block to single level cell mode when the most significant bit fails programming.

Dynamic bit line voltage control balances programming speed and reliability by adjusting potentials per loop count.

Series-configured wordline and load capacitances charged by a low voltage pump reduce recovery time without increasing power consumption or silicon area.

Controller tracks erase counts to schedule worn blocks for non-use, preventing bit errors from uneven wear.

Voltage sustaining block applies program sustaining voltage to interconnections overlapping junction regions.

Dynamic voltage switching reduces leakage current while maintaining fast transition rates to meet performance specifications.

Segmenting 3D memory into distinct computing and storage regions reduces latency and improves performance in computing-in-memory applications.

Multi-layer 3D NAND flash executes vector-matrix multiplication using selection voltages, reducing data transfer energy while maintaining computation accuracy.

Precharge voltage applied to unselected memory cells reduces programming disturb effects while enabling higher programming voltages for stubborn cells.

Programming edge cells with distinct threshold voltage distributions to compensate for residual charge effects in NAND flash memory arrays.

Dynamic stage control in the charge pump reduces peak current and power consumption by adjusting active pump units based on real-time input current levels.

Fractional bit memory cells store partial bit charges to boost density while a controller maps these states to accurate integer outputs.

A shunt line with a switching component selectively couples memory cell plates to digit lines, reducing induced voltages on unselected cells.

Weighted K-means clustering compresses NAND flash read threshold history tables, reducing storage volume while minimizing quantization errors.

Dynamic alternating activation of signal lines minimizes capacitive coupling effects, reducing power consumption without increasing chip area.

An adaptive moving read reference table orders entries by priority to recover from non-volatile memory read errors.

A non-volatile memory device assigns redundant rows to defective planes and loads their content into a volatile buffer for faster access.

A charge pump circuit uses a body bias circuit to reduce transistor threshold voltage and leakage current.