Hot Carrier Programming in 3D NAND Flash Memory
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Solution Overview
Problem
The increasing density of flash memory cells leads to cell-to-cell interference, limiting density growth, and high voltage requirements in NAND architecture increase manufacturing complexity and costs, while program disturb in three-dimensional arrays further complicates programming operations.
Innovation Solution
A three-dimensional array of memory cells using hot carrier generation assisted Fowler-Nordheim tunneling with self-boosting to inhibit disturb in unselected cells, employing floating body dual gate memory cells and specific voltage configurations to control hot-carrier programming and reduce program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fowler-Nordheim tunneling is used for programming in NAND architecture, then programming can be achieved, but high voltages (around 20 volts) are required which increase device complexity and manufacturing costs
Solution Approach 1:
The patent changes the voltage parameter from high voltage (20V) to low voltage operation by implementing hot carrier injection mechanisms. This allows programming to occur at lower voltages, eliminating the need for high voltage transistors and reducing device complexity while maintaining programming capability
Solution Approach 2:
The patent replaces the conventional Fowler-Nordheim tunneling mechanism with hot carrier injection mechanisms. This substitution enables programming without requiring high voltage transistors, thereby reducing device complexity and manufacturing costs while maintaining effective programming functionality
2Quantity of substance
If floating gate memory cells are used to increase density, then storage capacity increases, but cell-to-cell interference occurs which limits further density growth
Solution Approach 1:
The patent extracts the charge storage function from the floating gate structure and implements it through hot carrier injection mechanisms. This separation eliminates the cell-to-cell interference problem inherent in floating gate technology while maintaining high density capability
Solution Approach 2:
The patent substitutes the floating gate charge storage mechanism with hot carrier injection into charge trapping layers. This replacement eliminates interference between adjacent cells while enabling higher density storage through the three-dimensional array architecture
3Quantity of substance
If three-dimensional arrays are implemented to increase capacity, then storage capacity increases in smaller volume, but program disturb in unselected cells complicates programming operations
Solution Approach 1:
The patent applies local quality by implementing selective hot carrier injection into specific charge trapping layers corresponding to selected word lines. This localized injection prevents program disturb in unselected cells while maintaining efficient programming in selected cells, thereby simplifying programming operations in three-dimensional arrays
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient low-voltage programming with reduced program disturb, simplifying manufacturing and lowering costs by eliminating the need for high voltage transistors and improving device reliability through lower operation voltages and reduced inter-word line dielectric breakdown.
Implementation Method 1
Hot carrier injection is memory technology suitable for low voltage programming operations
Implementation Method 2
The programming processes typically rely on Fowler-Nordheim (FN) tunneling
Data Source
AI summary
A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.


