Multi-Circuit Control System for NAND Flash Status Reading

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Solution Overview

Problem

In multi-circuit systems, such as memory systems, the master circuit needs to read status information from multiple slave circuits, which currently requires sending individual read commands and receiving status information one by one, leading to inefficiencies and reduced performance when dealing with a large number of slave circuits.

Innovation Solution

A multi-circuit control system where a first circuit provides a read clock signal, and multiple second circuits are sequentially coupled in series, each equipped with at least one data shifter to load and shift out status information according to the read clock signal, or through a parallel transmission scheme.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the master circuit sends status information read commands one by one to each slave circuit, then the status information of each slave circuit can be read accurately, but the time consumption increases significantly when there are too many slave circuits

Engineering Contradiction:
Improvestatus information reading accuracyVSAvoidtime consumption for reading status information
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges multiple slave circuits into a daisy-chain connected structure where status information from multiple slaves is aggregated and transmitted through a single communication interface. The master circuit sends a single read command that triggers all slaves to shift their status information in sequence through the chain, combining multiple reading operations into one unified transmission process.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the status information transmission into sequential stages along the daisy chain. Each slave circuit's status information is divided into separate data bits that are shifted through successive circuits in the chain, allowing parallel preparation of status data while maintaining sequential transmission through a single interface.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If individual read commands are sent to each slave circuit, then the communication protocol remains simple, but the system working performance decreases due to time waste

Engineering Contradiction:
Improvecommunication protocol complexityVSAvoidsystem working performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements preliminary action by having each slave circuit pre-load its status information into shift registers before the read operation begins. When the master sends the read command, all status information is already prepared and can be shifted through the daisy chain immediately, eliminating command overhead for each slave while maintaining simple protocol structure.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250087253A1Multi-circuit control system and reading method for status information thereof
Publication Date: 2025.03.13 MACRONIX INTERNATIONAL CO LTD
  • US20250087253A1 patent drawing
  • US20250087253A1 patent drawing
  • US20250087253A1 patent drawing

AI summary

Disclosed are a multi-circuit control system and a reading method for status information thereof. The multi-circuit control system includes a first circuit and N second circuits. The second circuit is, for example a three dimensional NAND flash memory circuit, and the multi-circuit control system provides a storage media with high-performance and high-capacity. The first circuit provides a read clock signal. The second circuits are coupled in series, and coupled to the first circuit. Each of the second circuits has at least one first data shifter. The at least one data shifter is used to load status information of each of the second circuits, and shift out each of the status information to a second circuit of a previous stage or the first circuit or the first chip obtains the status information of each of the second circuits through a parallel transmission scheme.