Memory Device Suspend-Resume Latency Control
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Solution Overview
Problem
Conventional memory devices experience increased latency during erase operations due to suspension events, leading to inefficient host responses and potential errors when higher priority operations are required.
Innovation Solution
Implement a method to dynamically determine a minimum resume latency based on operating temperature and program-erase cycles (PECs) to optimize erase operations, allowing for efficient suspension and resumption of erase operations without increasing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the erase operation is suspended to allow higher priority operations, then the responsiveness to host requests is improved, but the erase latency increases
Solution Approach 1:
The patent implements dynamic suspend-resume-go control for erase operations, allowing the system to adaptively suspend erase operations when higher priority host requests arrive and automatically resume them when appropriate. This dynamic control mechanism enables the memory device to balance between responding to host requests and completing erase operations, improving overall system responsiveness without permanently delaying erase tasks.
2Productivity
If the erase operation is resumed immediately after suspension, then the productivity is improved, but the reliability decreases due to potential erase errors
Solution Approach 1:
The patent implements a preliminary waiting period (minimum resume latency) after suspend events before allowing resume operations. This preliminary action ensures that the memory block has sufficient time to stabilize after suspension, preventing erase errors that would occur with immediate resumption. The controller dynamically determines when it is safe to resume based on this minimum latency requirement, thus maintaining reliability while still enabling relatively quick resume operations.
3Adaptability or versatility
If multiple suspensions are allowed during erase operations, then the adaptability to host requests is improved, but the complexity of error management increases
Solution Approach 1:
The patent implements a feedback mechanism where the controller monitors the number of suspensions during erase operations and dynamically adjusts the minimum resume latency based on the vulnerability of the memory block. When multiple suspensions occur, the system uses feedback from suspension counters and memory block status to determine appropriate latency values, preventing error accumulation while managing multiple host requests. This feedback-based approach simplifies error management by providing clear decision criteria for resume timing.
Data Source
AI summary
The memory device includes an array of memory cells that are arranged in word lines and are programmed to contain data. Circuitry is configured to erase the memory cells of the memory block in an erase operation. During erase, the circuitry is configured to begin an erase operation to erase the memory cells and suspend the erase operation for a first suspension. After the first suspension is completed, the circuitry is configured to resume the erase operation. The circuitry is then configured to receive an instruction to suspend the erase operation for a second suspension and dynamically determine a minimum resume latency based on a vulnerability of the memory block to erase errors. Only after the minimum resume latency has passed following the step of resuming the erase operation after the first suspension is completed, the circuitry is configured to suspend the erase operation for the second suspension.