Flash Memory Programming Method for Multi-Bit Data
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Solution Overview
Problem
Conventional flash memory devices experience longer programming times for most significant bits (MSBs) due to sequential performance of Case1, Case2, and Case3 programming operations, which leads to increased coupling effects and inefficiencies in threshold voltage distribution.
Innovation Solution
Implementing a method that programs memory cells into provisional states based on least significant bits (LSBs) and MSBs using different programming modes, allowing for simultaneous programming of multiple states during one operation period, with a voltage generator and page buffer to regulate verify-read voltages and program controllers to optimize MSB programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential programming of Case1, Case2, and Case3 is performed for MSB, then programming completeness is achieved, but programming time increases and coupling effects worsen
Solution Approach 1:
The patent merges Case1 and Case2 programming operations into a single simultaneous programming stage. Memory cells are divided into first and second groups, where Case1 is performed on the first group and Case2 is performed on the second group at the same time, eliminating the sequential execution delay between these two cases while ensuring complete MSB programming.
2Reliability
If sequential programming of Case1, Case2, and Case3 is performed for MSB, then programming completeness is achieved, but coupling effects between adjacent cells increase
Solution Approach 1:
The patent merges Case1 and Case2 programming operations into a single simultaneous programming stage. Memory cells are divided into first and second groups, where Case1 is performed on the first group and Case2 is performed on the second group at the same time, eliminating the sequential execution delay between these two cases while ensuring complete MSB programming.
Solution Approach 2:
The patent segments memory cells into different groups (first group for Case1, second group for Case2) that can be programmed simultaneously. This segmentation allows parallel processing of different programming cases, reducing the total programming time and minimizing the duration during which coupling effects can occur between adjacent cells.
3Manufacturing precision
If incremental step pulse programming is used for MLC, then threshold voltage distribution is controlled, but programming loops increase
Solution Approach 1:
The patent merges Case1 and Case2 programming operations into a single programming loop by simultaneously executing them on different memory cell groups. This approach maintains the precise threshold voltage distribution control of ISPP while reducing the total number of programming loops required, as both cases are completed in parallel rather than sequentially.
Data Source
AI summary
Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data representing at least one of first through fourth states and including most significant bits and least significant bits. The method includes programming the plural memory cells into a provisional state according to the least significant bit, and programming the plurality of memory cells into the second through fourth states from the first and provisional states according to the most significant bit. Programming the plurality of memory cells into the second through fourth states includes simultaneously programming the plurality of memory cells at least partially into at least two states during one programming operation period.