Nonvolatile Memory Data Transfer Clock Synchronization
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Solution Overview
Problem
Nonvolatile semiconductor memory devices with both eight-bit and sixteen-bit data transfer functions face limitations in data transfer speed, as they can only transfer one eight-bit data in a transfer cycle period, hindering high-speed data transfer.
Innovation Solution
The implementation of a nonvolatile semiconductor memory device with a data transfer system that synchronizes data transfer with a second clock signal having twice the cycle of a first clock signal, allowing for simultaneous transfer of multiple bits, enabling faster data transfer by controlling internal operations to match sixteen-bit data transfer speeds for eight-bit data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a nonvolatile semiconductor memory device is arranged with both eight-bit data transfer function and sixteen-bit data transfer function using the same chip, then the device can be managed within the same chip regardless of I/O construction, but only one eight-bit data can be transferred in one transfer cycle period, resulting in low data transfer speed
Solution Approach 1:
The data transfer function is segmented into two independent transfer sections: an eight-bit data transfer section and a sixteen-bit data transfer section. Each section operates independently with its own clock signal, allowing simultaneous operation. The eight-bit transfer section uses a first clock signal while the sixteen-bit transfer section uses a second clock signal with twice the cycle, enabling the eight-bit section to complete two transfer cycles while the sixteen-bit section completes one, thereby achieving high-speed transfer for eight-bit data without affecting sixteen-bit transfer capability.
2Ease of operation
If data transfer is synchronized with a clock signal having a single cycle period, then the transfer operation is simple to control, but multiple eight-bit data cannot be transferred simultaneously, limiting data transfer efficiency
Solution Approach 1:
The invention employs periodic action by using two different clock signals with different cycle periods. The first clock signal has a standard cycle period for eight-bit data transfer, while the second clock signal has twice the cycle period for sixteen-bit data transfer. This periodic differentiation allows the system to optimize transfer speed for eight-bit data by completing two transfer cycles in the time it takes the sixteen-bit section to complete one cycle, thereby improving overall data transfer efficiency while maintaining simple control through synchronized clock management.
Data Source
AI summary
A nonvolatile semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines, a data program control section which programs a plurality of first multi-bits data each having a first number of bits, or a plurality of second multi-bits data each having a second number of bits twice that of said first multi-bits data, to said plurality of memory cell arrays, a page buffer circuit which stores said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said word lines from said plurality of memory cell arrays, a data transfer section which transfers said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said second number of bits from said page buffer circuit synchronized with a second clock signal having a cycle which is twice that of a first clock signal, and a data output section which receives said data from said data transfer section and outputs externally said data in synchronization with said first clock signal.