Page Buffer Structure for Non-Volatile Memory Bit Line Load Reduction
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Solution Overview
Problem
As the line width of fabrication processes decreases and integration levels increase in non-volatile memory devices, the capacitance between bit lines increases, leading to a higher load on each bit line, which existing page buffer structures struggle to manage effectively.
Innovation Solution
A non-volatile memory device with a page buffer structure featuring two registers, one for upper and one for lower memory cells, and a data I/O unit that enables multi-level cell programming using only one register, reducing the load on bit lines by centralizing the page buffer and connecting memory cell blocks in both directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the line width of fabrication process decreases and integration level increases, then memory capacity and integration are improved, but capacitance between bit lines increases and load on each bit line increases
Solution Approach 1:
The memory cell array is divided into multiple blocks (first memory cell block, second memory cell block, etc.) that can be independently accessed and programmed. This segmentation allows the page buffer to handle smaller subsets of cells at a time, reducing the capacitive load on bit lines during programming operations while maintaining high overall memory capacity through the combined blocks.
2Device complexity
If a single register is used for multi-level cell programming, then device complexity is reduced, but the register becomes vulnerable and programming reliability decreases
Solution Approach 1:
Data to be programmed is first loaded into the register in advance before the actual programming operation begins. This preliminary action allows the register to be prepared with the correct data pattern, and the programming process to proceed systematically through multiple verify operations at different voltage thresholds, improving reliability without requiring multiple registers.
3Object-affected harmful factors
If page buffer is centralized and memory cell blocks are connected in both directions, then load on bit lines is reduced, but device structure becomes more complex
Solution Approach 1:
The page buffer is positioned at a specific location with non-symmetric connections to memory cell blocks in different directions. This asymmetric layout optimizes the bit line routing to minimize capacitance and load, while the page buffer itself maintains a relatively simple internal structure with a single register, balancing structural complexity with performance benefits.
Data Source
AI summary
A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data to be programmed into cells included in a second memory cell block group, or reads and stores data of a corresponding memory cell. The data I/O unit inputs specific data to the first register and the second register, or outputs data stored in the first register and the second register.