3D Flash Memory Back Gate Structure for Leakage Control
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Solution Overview
Problem
Conventional three-dimensional flash memory devices experience degradation in cell characteristics and reliability as the number of vertical memory cells increases, leading to reduced performance and reliability.
Innovation Solution
The implementation of a back gate structure within the channel layer, where a pass voltage is applied to form or boost the channel, improving cell characteristics and reliability by preventing leakage currents and enhancing program and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertical memory cells is increased to improve storage capacity, then the degree of integration is improved, but cell characteristics and reliability are degraded
Solution Approach 1:
The channel layer is segmented into multiple regions along the vertical direction, with each region having its own independently controllable gate structure. This segmentation allows selective control of charge injection into different memory cell regions, preventing unintended programming and improving reliability while maintaining high integration.
Solution Approach 2:
Different gate structures are provided at different vertical positions of the channel layer, with each gate having different electrical characteristics suited for its specific function. The first gate structure is optimized for program operations while the second gate structure is optimized for erase operations, allowing local optimization of cell characteristics and reliability.
2Device complexity
If conventional gate control is used in vertically stacked memory cells, then device complexity is reduced, but leakage currents occur leading to unintended programming
Solution Approach 1:
The gate control is segmented into multiple independent gate structures positioned at different vertical levels. Each gate can be independently controlled to prevent leakage currents from affecting adjacent memory cell regions, thereby eliminating unintended programming while maintaining manageable device complexity.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between different gate structures and between gates and charge storage layers. These intermediaries electrically isolate different control regions, preventing harmful leakage currents while allowing each gate to function independently.
3Speed
If higher voltages are applied to improve program speed, then program speed is improved, but lateral diffusion of electrons occurs reducing reliability
Solution Approach 1:
The gate structures are designed with different local electrical characteristics - the first gate structure has parameters optimized for rapid program injection while the second gate structure has parameters optimized for preventing electron diffusion. This local optimization allows high program speed without sacrificing reliability.
Solution Approach 2:
The second gate structure is positioned and configured to preemptively counteract the lateral diffusion of electrons that would otherwise occur during high-voltage program operations. By applying appropriate voltages to this gate structure during programming, electron diffusion is prevented before it can degrade reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The back gate structure enhances the program speed, increases threshold voltages, and improves the overall reliability of memory cells by preventing unintended programming and lateral diffusion of electrons, thus maintaining cell characteristics and reliability.
Implementation Method 1
The flash memory device electrically programs/erases data by using the F-N (Fowler-Nordheim) tunneling or the hot electron injection.
Implementation Method 2
The flash memory device electrically programs/erases data by using the F-N (Fowler-Nordheim) tunneling or the hot electron injection.
Data Source
AI summary
Disclosed is a three-dimensional flash memory including a back gate, which includes word lines extended and formed in a horizontal direction on a substrate so as to be sequentially stacked, and strings penetrating the word lines and extended and formed in one direction on the substrate. Each of the strings includes a channel layer extended and formed in the one direction, and a charge storage layer extended and formed in the one direction to surround the channel layer, the channel layer and the charge storage layer constitute memory cells corresponding to the word lines, and the channel layer includes a back gate extended and formed in the one direction, with at least a portion of the back gate surrounded by the channel layer, and an insulating layer extended and formed in one direction between the back gate and the channel layer.


