Nonvolatile Memory Voltage Drop Reduction
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Solution Overview
Problem
As the integration of flash memory devices increases, voltage drop of the program voltage occurs due to parasitic capacitance, leading to dispersed resistance distribution in nonvolatile memory cells, even when a high-level program voltage is applied, resulting in ineffective data programming.
Innovation Solution
A nonvolatile memory device with a block switching unit and a voltage sustaining block that applies a program sustaining voltage greater than or equal to the threshold voltage of pass transistors to interconnections overlapping the junction regions, reducing parasitic capacitance and maintaining the operation signal across the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration degree of flash memory devices is increased, then storage capacity is improved, but voltage drop of program voltage occurs due to parasitic capacitance
Solution Approach 1:
The patent applies a program sustaining voltage to the bit line before and during the programming operation to preemptively counteract the voltage drop caused by parasitic capacitance. This preliminary action ensures that the bit line maintains the required high voltage level throughout the programming process, resolving the contradiction between increased integration (which increases parasitic capacitance) and voltage maintenance.
Solution Approach 2:
The patent changes the voltage parameter by introducing a program sustaining voltage that is maintained at a high level (e.g., VLCH or VPP) during the programming operation. This parameter change compensates for the voltage drop effect, allowing the system to maintain proper programming voltage levels despite increased parasitic capacitance from higher integration density.
2Ease of operation
If program voltage is applied through pass transistors, then data programming is enabled, but parasitic capacitance at junction regions causes voltage drop
Solution Approach 1:
The patent applies the program sustaining voltage to the bit line in advance and maintains it throughout the programming operation. This preliminary and sustained voltage application compensates for the parasitic capacitance effect at the pass transistor junction regions, ensuring that sufficient voltage reaches the memory cell for effective programming while maintaining ease of operation.
3Power
If high-level program voltage is applied, then programming capability is improved, but voltage drop reduces the actual voltage at memory cell
Solution Approach 1:
The patent applies the program sustaining voltage preliminarily and maintains it at a high level (VLCH or VPP) throughout the programming operation. This ensures that even when voltage drop occurs due to parasitic capacitance, the actual voltage at the memory cell remains sufficient for effective programming, thus maintaining programming capability while compensating for energy loss.
Solution Approach 2:
The patent changes the voltage parameter by introducing a program sustaining voltage that compensates for the expected voltage drop. This parameter adjustment ensures that the net voltage at the memory cell remains at the required level for effective programming, resolving the contradiction between applied power and actual voltage delivery.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, ensuring that the program voltage is maintained at the required level, preventing voltage drop and improving data programming accuracy in nonvolatile memory devices.
Implementation Method 1
The voltage drop of the program voltage may be caused by parasitic capacitance generated in the nonvolatile memory devices
Data Source
AI summary
A nonvolatile memory device includes a block switching unit which transmits an operation signal to a memory cell array, and a voltage sustaining block which provides a voltage to sustain the operation signal to an arbitrary interconnection overlapping the block switching unit.