Fractional Bit Memory Cell Programming and Integer Output
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Solution Overview
Problem
Conventional flash memory devices struggle to efficiently represent and store fractional numbers of bits, limiting their ability to store data in a compact and accurate manner, especially when trying to output integer numbers of bits from cells programmed to fractional states.
Innovation Solution
The implementation of a method that allows memory cells to be programmed to threshold voltage levels representing fractional numbers of bits, with a fractional bit controller combining data from multiple cells to output integer bits, using a data conversion table to map fractional bit states to integer representations, and employing error correction codes to handle invalid combinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are programmed to represent more than two data states (MLC), then memory density increases, but the ability to accurately represent and output integer numbers of bits deteriorates
Solution Approach 1:
The memory cell population is segmented into multiple groups, where each group is programmed to a specific threshold voltage level representing a different fractional number of bits (e.g., 1.5 bits, 2.5 bits). This segmentation allows the system to store varied information densities across different cell groups while maintaining accurate integer bit output through combination of fractional representations.
Solution Approach 2:
Fractional bit representations from multiple memory cells are nested and combined together to form complete integer bit outputs. For example, two cells each storing 1.5 bits can be combined to produce a 3-bit integer output, with the fractional portions nesting together to form the complete integer representation.
2Productivity
If memory cells store fractional numbers of bits, then data storage efficiency improves, but device complexity increases due to need for conversion and error correction
Solution Approach 1:
Error correction codes are pre-calculated and stored alongside the fractional bit data in the same memory cells. During read operations, the error correction data is automatically retrieved and applied to correct any invalid combinations before conversion to integer bits, eliminating the need for separate error correction hardware or processing steps.
Solution Approach 2:
A conversion table serves as an intermediary structure that maps fractional bit combinations from multiple cells to their corresponding integer bit representations. This table pre-defines all valid and invalid combinations, allowing the system to efficiently convert fractional representations to integer outputs while automatically identifying and correcting errors through the pre-stored mapping.
3Measurement precision
If multiple memory cells are combined to output integer bits, then data accuracy improves, but the number of operations and processing time increases
Solution Approach 1:
All possible fractional bit combinations from multiple cells are pre-calculated and stored in conversion tables during manufacturing or initialization. During actual read operations, the system simply looks up the pre-computed mapping from fractional to integer representations, avoiding real-time complex calculations and significantly reducing processing time while maintaining high data accuracy.
Data Source
AI summary
Methods, devices, modules, and systems for programming memory cells are disclosed. One method embodiment includes storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. The method also includes storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.