Semiconductor Storage Bit Line Control Circuit
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Solution Overview
Problem
The miniaturization of NAND flash memory has led to decreased cell current and increased mutual interference between bit lines, degrading read, write, and erase characteristics due to capacitive coupling, necessitating improved bit line control mechanisms.
Innovation Solution
The semiconductor storage device incorporates a bit line control circuit with clamp transistors, sense amplifiers, and accelerators to manage bit line potentials, allowing for accelerated charging and reduced interference by controlling connections between bit lines and sense amplifiers based on adjacent data latch section signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturization is increased to reduce device size, then device integration is improved, but cell current decreases and mutual interference between bit lines increases
Solution Approach 1:
The patent divides the bit line control into independent segments by providing separate clamp transistors for each bit line. This segmentation allows individual control of each bit line's potential, preventing mutual interference while maintaining miniaturization benefits. Each bit line can be independently recovered to its original potential without being affected by adjacent bit lines.
Solution Approach 2:
The patent introduces clamp transistors as intermediary elements between bit lines and sense amplifiers. These clamp transistors act as mediators that control the connection between bit lines and sense amplifiers, enabling accelerated charging when needed while preventing harmful capacitive coupling during normal operation. The switch circuit connected to data latch sections provides additional intermediary control based on read completion status.
2Volume of moving object
If miniaturization is increased to reduce device size, then device integration is improved, but mutual interference between bit lines increases
Solution Approach 1:
The patent extracts the harmful capacitive coupling effect by introducing clamp transistors that can disconnect adjacent bit lines from each other. By taking out the harmful interaction path through controlled disconnection, the patent eliminates mutual interference while preserving the compact device structure enabled by miniaturization.
Solution Approach 2:
The patent applies preliminary anti-action by pre-charging bit lines to their original potential using clamp transistors before read operations begin. This preliminary action counteracts the harmful capacitive coupling that would otherwise occur during miniaturized operation, preventing mutual interference before it can degrade read characteristics.
3Speed
If bit line charging is accelerated for all lines, then read speed is improved, but overcharging occurs and write/erase characteristics degrade
Solution Approach 1:
The patent makes the bit line charging process dynamic by using switch circuits controlled by data latch section signals. The connection between clamp transistors and bit lines is dynamically adjusted based on whether adjacent reads are completed, allowing accelerated charging only when safe. This dynamic control prevents overcharging while maintaining high read speed, and preserves write/erase characteristics by avoiding unnecessary charging during those operations.
Solution Approach 2:
The patent implements feedback control by using data latch section signals to control the switch circuits that regulate bit line charging. The system monitors the status of adjacent read operations and adjusts the charging behavior accordingly, providing feedback-based prevention of overcharging. This feedback mechanism ensures that accelerated charging is applied only when it will not harm write or erase characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances read speed and accuracy by accelerating bit line charging only for lines with completed reads, preventing overcharging and improving overall storage device performance.
Implementation Method 1
The recovery time depends on the capacitive coupling between the bit line and an adjacent bit line or a second adjacent bit line
Data Source
AI summary
According to one embodiment, a device includes transistors each with a path connected to a bit line, and circuits each includes a switch, the circuit being connected to the bit line. The device includes a amplifier connected to the transistor and to the circuit, and a latch connected to the amplifier to hold first data before read is carried out on a cell and to hold second data if a current equal to or a larger than a predetermined value flows via the bit line. In the device, the switch is turned on or off depending on data held in another latch located adjacently in a direction of the word lines, to control a connection between the bit line and connected to another bit line the amplifier via the circuit.