Edge Cell Vt Distribution for NAND Flash Reliability
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Solution Overview
Problem
Flash memory devices with multilevel cells (MLCs) face reliability issues due to slow erase effects, which lead to increased difficulty in distinguishing between adjacent data states, resulting in reduced data read and retrieval reliability, particularly affecting edge cells in NAND array architectures.
Innovation Solution
The method involves programming edge cells within a different threshold voltage (Vt) distribution than non-edge cells, adjusting sensing voltages and Vt distributions to compensate for residual charge left on edge cells during erase operations, thereby enhancing data state recognition and reducing erase verify failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are coupled in series in a NAND array architecture to achieve high memory density, then the memory density increases, but edge cells are affected by slow erase effects leading to reduced data read and retrieval reliability
Solution Approach 1:
The patent applies local quality by implementing different threshold voltage distributions for edge cells versus non-edge cells. Edge cells, which are adjacent to select gate transistors and suffer from slow erase effects, are programmed into a second Vt distribution that is shifted relative to the first Vt distribution used for non-edge cells. This localized adjustment compensates for the different erase characteristics of edge cells while maintaining high memory density through the series-coupled NAND architecture.
2Quantity of substance
If multilevel cells are used to store multiple data states by using different threshold voltage levels, then the memory capacity increases, but the difference between adjacent Vt distributions becomes very small making it difficult to distinguish between adjacent data states
Solution Approach 1:
The patent applies parameter changes by adjusting the threshold voltage distribution parameters specifically for edge cells. By shifting the second Vt distribution relative to the first Vt distribution, the patent modifies the voltage margins and separation between adjacent data states for edge cells, compensating for the reduced distinguishability caused by slow erase effects while maintaining the multilevel cell capacity.
3Device complexity
If edge cells are programmed within the same threshold voltage distribution as non-edge cells, then the programming process is simplified, but erase verify operations fail due to residual charge from slow erase effects
Solution Approach 1:
The patent implements local quality by creating a distinct second Vt distribution for edge cells that differs from the first Vt distribution used for non-edge cells. This localized differentiation ensures that edge cells, which experience slow erase effects and retain residual charge, are programmed to threshold voltages that account for this behavior, thereby enabling successful erase verify operations while keeping the overall programming process manageable.
Data Source
AI summary
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a number of memory cells coupled in series between a first and second select gate transistor where edge cells are coupled adjacent to the select gate transistors and non-edge cells are coupled between the edge cells. The method includes programming a non-edge cell within a first threshold voltage (Vt) distribution. The method also includes programming an edge cell within a second Vt distribution, wherein the first and second Vt distributions correspond to a same one of a number of data states, and wherein the second Vt distribution is different than the first Vt distribution for at least one of the number of data states.