Memory Device Bit Line Voltage Control for Programming Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face inefficiencies in program performance due to limitations in voltage control and verification processes, which affect the reliability and speed of data programming in non-volatile memory cells.
Innovation Solution
A memory device with a peripheral circuit and control logic that performs multiple program loops, including program and verify operations, where the bit lines are controlled to reach specific voltage levels based on a program loop count, optimizing the reference and target voltage levels to enhance programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single high voltage level is applied to bit lines during programming, then programming speed is improved, but peak current increases and reliability deteriorates
Solution Approach 1:
The bit line voltage is divided into multiple levels (first voltage level during program operation, second voltage level during verify operation) instead of using a single voltage level. This segmentation allows the system to achieve fast programming with high voltage while ensuring reliability with lower voltage during verification, thus resolving the contradiction between speed and reliability
Solution Approach 2:
The bit line voltage is dynamically adjusted based on the operation phase (program or verify) and the program loop count. The voltage transitions from a first voltage level to a second voltage level, and the reference voltage is dynamically determined according to the program loop count, enabling adaptive voltage control that balances speed and reliability
2Productivity
If voltage levels are increased to improve programming efficiency, then program performance is improved, but current consumption increases
Solution Approach 1:
The patent changes the voltage parameter dynamically based on the program loop count. The reference voltage level is determined differently according to the program loop count, allowing the system to optimize voltage levels for each programming stage. This parameter change enables improved program performance while controlling current consumption by using appropriate voltage levels at different programming stages
3Reliability
If multiple program loops are performed with fixed voltage levels, then programming completeness is improved, but programming time increases
Solution Approach 1:
The patent implements periodic program-verify loops with dynamically adjusted voltage levels. Each program loop uses a reference voltage determined by the loop count, creating a periodic pattern of operations with varying parameters. This periodic action with dynamic voltage adjustment ensures programming completeness while reducing total programming time compared to fixed voltage levels
Solution Approach 2:
The reference voltage is dynamically determined according to the program loop count, making the voltage levels adaptive to the programming progress. This dynamic adjustment allows the system to complete multiple program loops efficiently by optimizing voltage levels at each stage, thereby reducing overall programming time while ensuring completeness
Data Source
AI summary
The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.