Selective Slow Programming for Flash Memory Vt Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory devices face challenges in generating narrow threshold voltage (Vt) distributions without reducing programming throughput, as methods like two-step programming or adjusting programming pulse voltages slow down all cells, including faster ones, thereby increasing programming time.
Innovation Solution
The selective slow programming method involves biasing the bit line of each cell only when it reaches a pre-verify voltage level, allowing faster cells to maintain normal programming speed while slowing down slower cells, thereby narrowing Vt distributions without reducing overall throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-step programming method is used to narrow Vt distributions, then Vt distribution narrowness is improved, but programming throughput is reduced
Solution Approach 1:
The patent applies local quality by differentiating programming speeds for different cells based on their individual characteristics. Instead of uniformly slowing down all cells, the system identifies faster cells and selectively applies reduced programming speeds only to those cells that have reached a pre-verify voltage threshold, while allowing slower cells to continue at normal speed. This localized approach narrows Vt distributions for faster cells without compromising overall programming throughput.
Solution Approach 2:
The patent implements dynamics by making the programming speed adaptive and variable rather than fixed. The programming speed is dynamically adjusted based on real-time monitoring of cell threshold voltage progress. When a faster cell reaches the pre-verify threshold, its programming speed is reduced; when slower cells are detected, they continue at normal speed. This dynamic adjustment allows the system to optimize Vt distribution narrowness while maintaining overall productivity.
2Manufacturing precision
If programming pulse step voltage is adjusted as cell approaches programmed state, then Vt distribution narrowness is improved, but programming throughput is reduced
Solution Approach 1:
The patent applies local quality by selectively adjusting programming pulse step voltage only for faster cells that have reached the pre-verify threshold, rather than uniformly reducing the step voltage for all cells. This localized adjustment narrows Vt distributions for the subset of faster cells without impacting the programming speed of slower cells, thereby maintaining overall throughput while achieving distribution narrowness.
Solution Approach 2:
The patent segments the memory cells into different groups based on their programming speed and threshold voltage progress. Faster cells that have reached the pre-verify threshold are separated from slower cells and receive different programming pulse treatment. This segmentation allows independent optimization of programming parameters for different cell subsets, achieving Vt distribution narrowness without sacrificing overall programming throughput.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre- verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre- verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.