Nonvolatile Memory Page Buffer Pre-Charging for Speed

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Solution Overview

Problem

The increasing number of bits stored per memory cell in nonvolatile memories leads to reduced operating speed due to the need for additional operations during data reading and programming.

Innovation Solution

The implementation of first and second page buffers with connected bit lines, where latch nodes are charged to specific voltages, and a sensing node is pre-charged to facilitate data dumping between latches, reducing coupling effects that prolong pre-charge times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of bits stored per memory cell is increased, then the storage capacity is improved, but the operating speed is reduced

Engineering Contradiction:
Improvestorage capacityVSAvoidoperating speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The sensing node is pre-charged before the actual read operation begins. This preliminary action prepares the sensing node in advance, allowing it to quickly respond when data is dumped from the latch during the read operation, thereby reducing the overall operation time and maintaining high operating speed despite increased storage capacity

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If additional operations are performed for reading and programming data, then the storage capacity is improved, but the operating speed is reduced

Engineering Contradiction:
Improvestorage capacityVSAvoidoperation time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The pre-charging of the sensing node is performed continuously and concurrently with other preparation operations rather than sequentially. This allows the useful action of preparing the sensing node to overlap with other operations, eliminating idle time and reducing the total operation time required for read and programming operations

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If latch nodes are charged to specific voltages, then the data storage reliability is improved, but the pre-charge time is prolonged

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidpre-charge time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The sensing node is pre-charged to the required voltage level before the actual data dumping operation begins. This preliminary charging action ensures that when data is dumped from the latch, the sensing node is already in the optimal state to quickly and reliably detect the data, thus maintaining reliability while minimizing the time penalty

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9947414B2Nonvolatile memory device and operating method thereof
Publication Date: 2018.04.17 SAMSUNG ELECTRONICS CO LTD
  • US9947414B2 patent drawing
  • US9947414B2 patent drawing
  • US9947414B2 patent drawing

AI summary

An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.