Variable Resistance Memory Programming with Segmented Currents
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in efficiently programming and verifying multi-bit data in variable resistance memory cells, particularly in ensuring that the actual resistance of programmed cells falls within intended resistance distributions, which affects data accuracy and storage efficiency.
Innovation Solution
A method is introduced for operating nonvolatile memory devices that involves providing sequential program currents to variable resistance memory cells, adjusting the current based on verification results to ensure the actual resistance resides within intended distributions, and classifying data into even and odd categories for precise programming and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single program current is applied to variable resistance memory cells to program multi-bit data, then the programming operation is simple and fast, but the actual resistance of programmed cells cannot be ensured to fall within intended resistance distributions
Solution Approach 1:
The patent segments the multi-bit data into even data and odd data, and applies different program currents (first program current for even data, second program current for odd data) to programmably set the resistance of variable resistance memory cells to different target resistance distributions. This segmentation allows precise control over the resistance distribution for each bit, ensuring that the actual resistance falls within intended ranges while maintaining a structured programming approach.
2Reliability
If program current is adjusted based on verification results to ensure resistance accuracy, then data storage reliability is improved, but the programming time and operational complexity increase
Solution Approach 1:
The patent applies preliminary verification after programming even data to determine whether the resistance of the variable resistance memory cell falls within a first reference resistance distribution. Based on this verification result, the program current is adjusted before programming odd data. This preliminary action ensures that resistance accuracy is established early, reducing the need for extensive re-programming and thereby limiting the time penalty despite the additional verification step.
3Manufacturing precision
If multiple program currents are used to program different bits of data, then resistance distribution accuracy is improved, but the number of programming operations and device complexity increase
Solution Approach 1:
The patent applies local quality by using different program currents tailored to specific programming needs: a first program current is used for programming even data to achieve a first target resistance distribution, while a second program current is used for programming odd data to achieve a second target resistance distribution. This localized approach to current application optimizes the resistance distribution accuracy for each bit position without requiring exhaustive programming operations across all cells uniformly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and efficiency of multi-bit data programming and reading in nonvolatile memory devices by iteratively adjusting program currents and categorizing data, thereby improving data storage reliability and reducing the risk of data loss during power interruptions.
Implementation Method 1
a nonvolatile memory device including first and second variable resistance memory cells connected to one of word lines
Data Source
AI summary
An operating method of a multi-bit-per-cell nonvolatile memory device, e.g., first and second variable resistance memory cells connected to one of word lines. The operating method may include receiving first to fourth data sequentially, providing a first program current to the first variable resistance memory cell to program the first and second data to the first variable resistance memory cell, and providing a second program current to the second variable resistance memory cell to program the third and fourth data to the second variable resistance memory cell after verifying whether an actual resistance of the programmed first variable resistance memory cell is within an intended resistance distribution.