3D Memory Fabrication via Segmented Patterning
Solution Overview
Problem
Conventional methods for fabricating three-dimensional cross point type semiconductor memory devices, such as ReRAM, require a large number of exposure steps and result in increased costs due to extensive use of double patterning technology, leading to explosive area increases in hookup regions and higher costs.
Innovation Solution
The method simplifies the fabrication process by reducing the number of exposure times for loop cuts and minimizing the area of dummy regions through simultaneous loop cuts for both word and bit lines, and by strategically positioning dummy memory cell structures to prevent dishing during chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technology is used to fabricate miniaturized memory devices, then manufacturing precision is improved, but device complexity and number of fabrication steps increase
Solution Approach 1:
The fabrication process is divided into distinct regions: a first region where double patterning is applied for high-precision memory cell formation, and a second region where simplified single patterning is used for hookup regions. This spatial segmentation allows each region to use the appropriate fabrication complexity level, reducing overall process complexity while maintaining where needed
Solution Approach 2:
Different fabrication approaches are applied to different regions based on their specific requirements. The first region (memory cell area) receives high-precision double patterning treatment, while the second region (hookup area) uses simpler single patterning. This local differentiation optimizes the balance between precision requirements and process complexity
2Manufacturing precision
If extensive double patterning is applied to all regions, then manufacturing precision is improved, but fabrication cost increases
Solution Approach 1:
The substrate is divided into two regions with different fabrication requirements. Double patterning is applied only to the first region where high precision is critical for memory cell functionality, while the second region uses cost-effective single patterning for interconnect formation, thereby reducing overall fabrication costs
Solution Approach 2:
The fabrication approach parameter changes spatially across the substrate. By adjusting the patterning method parameter (double vs. single patterning) based on location-specific requirements, the process achieves cost optimization without compromising the precision needed in critical areas
3Manufacturing precision
If dummy regions are added to prevent dishing during polishing, then manufacturing precision is improved, but the area occupied by dummy structures increases
Solution Approach 1:
The dummy structures are merged with the interconnect lines in the second region. The dummy bit lines are formed alongside actual bit lines, and dummy word lines are formed alongside actual word lines, allowing the dummy structures to serve dual purposes: preventing dishing during CMP and functioning as part of the interconnect system
Solution Approach 2:
The dummy structures serve multiple functions simultaneously: they act as placeholders to maintain uniform polishing pressure and prevent dishing, while also serving as functional interconnect elements (dummy bit lines and dummy word lines) that can be connected to peripheral circuits. This multi-functionality eliminates the need for separate dummy regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall fabrication cost and simplifies the process by decreasing the number of exposure times and dummy region area, thereby improving the efficiency and reducing the cost of producing three-dimensional cross point type memory devices.
Implementation Method 1
performing a chemical mechanical polishing to remove the first dummy bit line and the first dummy word line
Data Source
AI summary
According to one embodiment, a method of fabricating a semiconductor memory device includes patterning a first memory cell layer and a first interconnect layer to form a first structure of a linear pattern in a first region and a second structure in a second region, forming a second interconnect layer and a second memory cell layer, and patterning the second memory cell layer and the second interconnect layer to form, in the first region, a third structure having a linear pattern and having a folded pattern immediately on the second structure. The method further includes removing the second memory cell layer and the second interconnect layer in the folded pattern, and the first memory cell layer of the second structure positioned under the folded pattern.