3D Memory Select Conductor Structure for RC Delay and Reliability
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor devices deteriorates as the number of stacked memory cells increases, necessitating improved structural design to enhance integration and performance.
Innovation Solution
The semiconductor device incorporates conductive layers and interlayer insulating layers alternately stacked with select conductors, outer and inner auxiliary conductors surrounding cell plugs, and select protrusions to form a robust select line structure, reducing RC delay and off-characteristics of source select transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stacked number of memory cells is increased to improve the degree of integration, then the area occupied by memory cells per unit area is reduced, but the operational reliability of the three-dimensional semiconductor device deteriorates
Solution Approach 1:
The select line is segmented into multiple conductors (first select conductor, second select conductor, third select conductor) that are spatially separated and independently configured. Each conductor serves a specific region (inner region, outer region, or both), allowing independent optimization of select characteristics without increasing the stacked number of memory cells, thereby maintaining reliability while supporting high integration
Solution Approach 2:
The patent transitions from a single-layer select line configuration to a multi-layer three-dimensional configuration. Select conductors are arranged at different vertical levels (first through third conductors at different heights) and horizontal positions (inner and outer regions), creating a spatially distributed select network that reduces interference and improves operational reliability in highly integrated 3D structures
2Reliability
If additional conductive layers are added to improve select line control, then RC delay and off-characteristics are reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The auxiliary conductor is designed to serve multiple functions simultaneously: it acts as a select line for outer memory cells, provides electrical connection between different select conductors through connection parts, and forms round parts that surround outer cell plugs for precise select control. This multi-functionality reduces the need for separate dedicated structures, thereby improving select line control without proportionally increasing device complexity
Solution Approach 2:
The patent merges the functions of multiple select lines into a single auxiliary conductor structure. The first, second, and third select conductors are electrically connected through the auxiliary conductor's connection parts, creating an integrated select network that achieves comprehensive select line control while reducing the total number of independent conductive layers required
Data Source
AI summary
A semiconductor device includes: conductive layers and interlayer insulating layers, which are alternately stacked; a select conductor spaced apart from the conductive layers; cell plugs penetrating the conductive layers, the interlayer insulating layers, and the select conductor; and an auxiliary conductor in contact with the select conductor.