3D Memory Array With Concentric Select Devices
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Solution Overview
Problem
Current memory device fabrication challenges include reducing size, increasing storage density, and lowering costs, particularly in two-dimensional arrays, where complex and costly processes are required to form three-dimensional memory arrays with select devices.
Innovation Solution
A three-dimensional memory array is designed with a stack of conductive lines separated by insulation, featuring conductive extensions perpendicular to the lines, with storage element material and select devices arranged concentrically around the extensions, reducing the need for complex etching or chemical mechanical polishing and allowing for increased memory cell current and tailored cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory arrays with select devices are formed using conventional fabrication processes, then memory density and storage capacity are improved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from two-dimensional memory arrays to three-dimensional memory arrays by stacking multiple levels of memory cells vertically. Conductive lines are arranged in multiple layers separated by insulation material, with conductive extensions extending perpendicular to the lines, creating a 3D cross-point architecture that increases memory density without proportionally increasing fabrication complexity
Solution Approach 2:
The patent implements a nested structure where storage element material is arranged around conductive extensions, and select devices are arranged around the storage element material, creating concentric cylindrical configurations. This nesting approach allows multiple functional components to be integrated in a compact vertical arrangement, improving memory density while using standard fabrication processes
2Ease of manufacture
If conventional two-dimensional memory arrays are used, then fabrication processes are simpler, but storage density and memory capacity are limited
Solution Approach 1:
The patent employs a three-dimensional cross-point architecture where word lines and bit lines extend in perpendicular directions through multiple vertical levels. This 3D arrangement allows memory cells to be stacked above and below each other, dramatically increasing storage density while maintaining compatibility with conventional planar fabrication processes
3Manufacturing precision
If extensive etching and chemical mechanical polishing are used to form 3D memory arrays with select devices, then memory cell structure precision is improved, but manufacturing cost and process time increase
Solution Approach 1:
The patent utilizes self-aligned fabrication processes where conductive extensions automatically form at precise locations through material deposition and patterning steps. The concentric arrangement of select devices around storage elements is achieved through sequential deposition of materials that self-align to previous layers, eliminating the need for complex etching and chemical mechanical polishing operations
Data Source
AI summary
Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.