Solid-State Devices TRIZ Cases

A semiconductor substrate integrates a sixth region surrounding avalanche diode pixels to electrically isolate charge carriers.

A phase-change memory element uses a tapered profile hardmask to define the material pedestal.

A microcavity OLED device uses a quarter wave stack mirror to tune cavity length and optimize light extraction efficiency.

A three-layer terminal structure in organic electroluminescence devices lowers electrical resistance through specific conductive film stacking.

A row control circuit applies stepped program voltages and adjusted pass voltages to manage charge injection in semiconductor memory cells.

Vertical holes in the pre-mold allow the molding member to fill and mechanically interlock, preventing separation under vibration.

A doped polymer substrate stabilizes thin film transistor electrical characteristics through controlled dopant concentration.

A dual-layer channel protective structure prevents oxygen detachment in oxide semiconductor thin film transistors.

A stacked imaging element uses vertically arranged photoelectric conversion sections to detect different wavelength bands without phase shift.

Organic encapsulation layer fills gaps in foldable OLED pixel definition regions to create a flat surface for subsequent inorganic coating.

A liquid crystal display fabrication method uses impurity-doped amorphous silicon patterns to minimize voltage drop across electrode structures.

Varying function layer thickness and bank taper angles per color element improves light extraction efficiency across red, green, and blue pixels.

Reverse tapered barrier rib expands electrode contact area to resolve aperture ratio and transmissivity trade-offs.

An embedded doped layer and contact structure discharge coupled charges above the buried oxide, eliminating back side bias effects in SOI devices.

Coating the susceptor with a silicon film prevents periphery etching in hydrogen atmospheres, maintaining SOI layer thickness uniformity.

Sidewall spacers on gate and interconnect structures enable sub-70nm feature sizing without requiring new equipment.

Ethynylene acene polymers resist oxidative doping to maintain stable current on/off ratios in ambient conditions without rigorous oxygen exclusion.

A buried word line connection pad structure enables uniform contact hole depths in semiconductor memory devices.

A three-dimensional non-volatile memory structure uses position-dependent blocking dielectric thickness to normalize programming speed across word lines.

Vertical stacking of conductive layers enables a single driver to control multiple memory blocks, reducing wiring complexity and signal delay.

Formula 1 heterocyclic compounds optimize HOMO-LUMO alignment to reduce driving voltage while maintaining high external quantum efficiency.

Stacked signal lines combine a metal layer with a light absorbing layer to maintain electrical conductivity while blocking ambient light reflection.

Local p-type impurity regions passivate dangling bonds at the substrate-gate oxide interface, suppressing dark current generation and preventing ghost images.

Raising the chip mounting area reduces encapsulant bead height, enabling closer nozzle proximity without obstructing active surfaces.

Dynamic pressure control reduces wasteful target material consumption during idle periods while maintaining readiness for extreme ultraviolet light generation.

A variable resistance memory device uses an oxygen barrier layer to inhibit gas migration between metal oxide layers.

Integrated lens array and light-shielding layers eliminate separate collimating films, reducing assembly complexity while improving fingerprint signal accuracy.

Segmented red and blue diode chips expand the emission spectrum to resolve color rendition limits in conventional lighting.

An etching stopper defines a channel width exceeding the shortest overlap distance, improving electron mobility without deteriorating the aperture ratio.

Segmenting the organic layer with specialized compounds resolves transport limitations, boosting efficiency and lifespan.

A display panel uses a height adjusting layer below the contact hole to reduce its opening area.

A rapid thermal annealing method adjusts light source intensity based on STI distribution density to ensure uniform process temperatures.

Adding a deep red phosphor with a longer emission peak to a BGR mixture resolves the trade-off between luminance intensity and color rendering properties.

Concentric select devices around conductive extensions in a 3D memory stack reduce fabrication complexity while increasing storage density.

A semiconducting material using divalent metal borate complexes with dialkylphosphine oxide matrix compounds to optimize electron injection.

Mandrel-based spacer patterning prevents non-vertical sidewalls and inconsistent shapes in photolithographically-patterned photoresist features.

Uniform gate dielectric in 3D memory select transistors reduces leakage currents, ensuring consistent threshold voltages and on-currents.

Layered optical control absorbs blue light within one-fifth of the active layer thickness to reduce color distortion from quantum efficiency changes.

Optical light guide arrays reduce afterpulsing and crosstalk by directing photons onto active SPAD areas via adhesive beads.

Sequential deposition etching forms tungsten floating gates in back side recesses, enhancing data retention and reducing thermal budget constraints.

Introducing a nanoporous layer reduces contact resistance and prevents current leakage by improving electrical connection reliability.

Annular protrusions and grooves on substrates prevent water ingress that corrodes OLED cathodes, extending device service life.

Floating anode regions boost reverse recovery speed without increasing leakage currents or threshold voltage.

A light-emitter mounting package uses a sloping recess wall and spaced metal layer to reflect emitted light.

A light emitting device uses multi-layer conductive patterns with exposed first layers for element mounting and covered second layers for external connectors.

Vertical stacking of resistive memory cells reduces cell area to 4F2, enabling high-density arrays without increasing lateral footprint.

A programmable resistive memory kernel confines the heating region within a dielectric spacer to reduce heat dissipation from electrodes.

A liquid crystal display array substrate uses a single masking process to form low-resistance data wirings.

LSSIM/T microscopy modulates laser scanning illumination temporally to create controllable spatial patterns for sub-diffractional lateral resolution.