4F2 Resistive Memory Cell in NAND Architecture
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Solution Overview
Problem
Current resistive memory technologies face challenges in achieving high density and small cell area configurations, limiting their scalability and efficiency in integrated circuit applications.
Innovation Solution
The development of a logical NAND memory architecture with two-terminal resistive switching memory cells, where each cell comprises a transistor in parallel with a resistive memory device, allowing for a 4F2 cell area configuration and enabling high-density memory arrays through advanced lithographic technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional resistive memory architectures are used, then memory storage capability is achieved, but cell area is large and density is low
Solution Approach 1:
The patent implements a three-dimensional vertical stack architecture where memory cells are stacked vertically over active areas, transitioning from conventional two-dimensional planar layouts to three-dimensional structures. This vertical stacking enables multiple memory cells to occupy the same footprint area, achieving 4F2 cell area and high density without increasing the lateral footprint.
Solution Approach 2:
The patent employs nested structures where control gates, tunnel barriers, and channel regions are arranged in concentric or layered configurations. The control gates wrap around or overlay the channel regions, and tunnel barriers are positioned between storage nodes and channels, creating nested functional units that maximize space utilization within the vertical stack.
2Quantity of substance
If cell area is reduced to increase density, then memory density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into discrete functional segments including separate control gates (first and second control gates), tunnel barriers, channel regions, and storage nodes. Each segment can be independently formed and controlled during fabrication, allowing precise manufacturing of individual components while maintaining the overall compact 4F2 cell structure.
Solution Approach 2:
By moving to three-dimensional vertical stacking, the patent achieves high density through the vertical dimension rather than compressing lateral dimensions. This approach maintains manufacturable feature sizes in the lateral plane while utilizing vertical space for multiple memory cell stacks, thereby reducing the impact of lithographic resolution limits.
3Quantity of substance
If high density configuration is implemented, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent employs control gates that serve multiple functions: they control charge injection into storage nodes, enable read operations through voltage modulation, and facilitate program/erase operations. The first and second control gates work together to provide both selection and data manipulation capabilities, reducing the need for separate dedicated structures for each function.
Solution Approach 2:
The patent combines selection transistors and storage elements into integrated vertical stacks where control gates, channels, and storage nodes are merged into compact three-dimensional units. Multiple memory cells share common bit lines and word lines, and adjacent stacks are electrically connected through shared conductive structures, reducing overall device complexity despite high density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density memory arrays with improved scalability and memory retention, longevity, and efficient read/write times, addressing the limitations of existing resistive memory technologies.
Implementation Method 1
RRAM stores information by controllably switching among distinct resistive states. Various theories have been proposed by the inventors to explain the phenomenon of resistive switching. In one such theory, resistive switching is a result of formation of a conductive structure within an otherwise electrically insulating medium.
Implementation Method 2
The conductive structure could be formed from ions, atoms that can be ionized under appropriate circumstances (e.g., a suitable electric field), or other charge carrying mechanisms.
Implementation Method 3
In other such theories, field-assisted diffusion of atoms can occur in response to a suitable electric potential applied to a resistive memory cell.
Implementation Method 4
In still other theories proposed by the inventors, formation of the conductive filament can occur in response to joule heating and electrochemical processes in binary oxides (e.g., NiO, TiO2, or the like)
Implementation Method 5
formation of the conductive filament can occur in response to joule heating and electrochemical processes in binary oxides (e.g., NiO, TiO2, or the like), or by a redox process for ionic conductors including oxides, chalcogenides, polymers, and so on.
Implementation Method 6
formation of the conductive filament can occur in response to joule heating and electrochemical processes in binary oxides (e.g., NiO, TiO2, or the like), or by a redox process for ionic conductors including oxides, chalcogenides, polymers, and so on.
Data Source
AI summary
A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4 F2 area. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.