3D Non-Volatile Memory With Variable Dielectric Thickness
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Solution Overview
Problem
Non-volatile memory devices face variations in programming speed due to differences in memory cell dimensions resulting from fabrication processes, leading to operational errors and data corruption.
Innovation Solution
Implementing 3D non-volatile memory arrays with varying word line gate lengths and blocking dielectric thicknesses based on memory hole diameters to normalize programming speed across memory cells, using a stack of alternating word lines and dielectric layers, and varying the thickness of the blocking dielectric to offset variances in memory hole diameter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to increase density, then memory capacity per die area is improved, but programming speed variation and operational errors increase
Solution Approach 1:
The patent applies local quality by making the blocking dielectric layer thickness position-dependent within the memory hole. Specifically, the blocking dielectric thickness is reduced at lower positions (deeper in the hole) where the hole diameter is smaller, and increased at upper positions where the hole diameter is larger. This local variation in dielectric thickness compensates for the non-uniform electric field distribution caused by tapered memory holes, thereby maintaining consistent programming speed across different cell positions while preserving high density.
2Quantity of substance
If memory cells are packed more closely to increase capacity, then die area efficiency is improved, but programming and reading errors increase
Solution Approach 1:
The patent implements local quality by varying the blocking dielectric thickness according to the local memory hole diameter. In densely packed arrays where holes are smaller and more tapered, the blocking dielectric is made thinner at lower positions to maintain appropriate electric field strength. This local adjustment ensures reliable programming and reading operations even in high-density configurations where uniform thickness would lead to operational errors.
3Ease of manufacture
If uniform blocking dielectric thickness is used, then manufacturing simplicity is maintained, but programming speed varies due to memory hole diameter variations
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through position-dependent blocking dielectric thickness. Rather than using a uniform thickness that would require complex post-fabrication adjustments, the dielectric layer is deposited with controlled thickness variation during the fabrication process itself. This approach maintains manufacturing feasibility while achieving consistent programming speed across the memory array.
Solution Approach 2:
The patent applies parameter changes by modifying the blocking dielectric thickness parameter as a function of position within the memory hole. The thickness parameter is specifically reduced at lower positions where the hole diameter is smaller, counteracting the enhanced electric field concentration in those regions. This parameter variation ensures uniform programming speed without requiring complex manufacturing processes.
Data Source
AI summary
A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.