Buried Word Line Connection Pad Fabrication
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Solution Overview
Problem
As semiconductor memory apparatuses become more integrated, the reduction in transistor channel length leads to short channel effects and increased parasitic capacitance, causing operational reliability issues and defects during fabrication, particularly in forming gate patterns and contact structures.
Innovation Solution
A method for fabricating semiconductor memory apparatuses with a buried word line structure, where a connection pad is formed in the isolation layer under the gate pattern in the peripheral region, allowing for increased processing margins and uniform contact hole depths to prevent defects and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length of the transistor is reduced to increase integration density, then the data storage capacity and degree of integration increase, but short channel effects and drain induced barrier lower occur which deteriorate operational reliability
Solution Approach 1:
The patent transitions from a planar two-dimensional channel structure to a three-dimensional vertical channel structure. The channel extends vertically through the substrate thickness, maintaining a longer effective channel length while occupying a smaller footprint area, thus resolving the contradiction between integration density and operational reliability
Solution Approach 2:
The patent changes the geometric parameters of the channel from horizontal extension to vertical extension. By making the channel depth equal to the substrate thickness and positioning electrodes at top and bottom surfaces, the channel length is maintained in the vertical dimension while reducing the horizontal footprint, thereby improving integration density without sacrificing reliability
2Reliability
If the doping concentration in the channel region is increased to maintain threshold voltage as channel length decreases, then the threshold voltage is maintained, but the electric field in the storage node junction increases which deteriorates refresh property
Solution Approach 1:
The patent changes the channel geometry from short horizontal length to long vertical length, allowing threshold voltage maintenance through geometric configuration rather than high doping concentration, thereby preserving refresh property
3Productivity
If the distance between bit line and word line is reduced to increase integration, then the degree of integration increases, but parasitic capacitance between bit line and word line increases which deteriorates operational margin of sense amplifier
Solution Approach 1:
The word line is repositioned from a planar structure in the same layer as bit lines to a buried structure extending vertically through the substrate. This vertical separation in the third dimension reduces parasitic capacitance between word lines and bit lines while maintaining high integration density
4Reliability
If a buried word line structure is used to reduce parasitic capacitance, then parasitic capacitance is reduced, but the gate pattern formation process becomes complex requiring separate formation steps for connection pads
Solution Approach 1:
The connection pad and gate pattern are merged into a single formation step using one photomask. The gate pattern photomask simultaneously defines both the gate electrode and the connection pad, eliminating separate formation steps and reducing fabrication process complexity while maintaining the buried word line structure's parasitic capacitance reduction benefits
Data Source
AI summary
A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.