LCD Array Substrate Single Masking Process and Diffusion Barrier
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Solution Overview
Problem
The existing liquid crystal display (LCD) fabrication process requires multiple masking processes, leading to increased production costs and yield degradation due to the need for expensive masks, and results in wavy noise from protruded active tails in data lines, which distort liquid crystal movement and cause screen artifacts.
Innovation Solution
A method for fabricating an array substrate using a single masking process with a half-tone or slit mask to form low-resistance data wirings and implementing a diffusion preventing layer with a metal tip to prevent copper diffusion, reducing the number of masking steps and improving channel precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masking processes are used to fabricate the array substrate, then the TFT structure can be formed with proper alignment, but the production cost increases and productivity decreases due to the need for expensive masks and multiple processing steps
Solution Approach 1:
The patent combines multiple masking processes into a single masking step by forming the active pattern, source/drain electrodes, and data line patterns simultaneously. This is achieved by depositing a conductive metal material layer that covers the entire substrate and then performing one photolithography process to pattern all three structures at once, eliminating the need for separate masking steps for each component.
Solution Approach 2:
The single masking process serves multiple functions: it defines the active pattern boundaries, forms the source and drain electrode patterns, and creates the data line patterns all in one operation. The photolithography step becomes a universal patterning tool that simultaneously controls the geometry of multiple TFT components, replacing the need for component-specific masking procedures.
2Manufacturing precision
If multiple masking processes are used to fabricate the array substrate, then the TFT structure can be formed with proper alignment, but the production cost increases due to the need for expensive masks
Solution Approach 1:
The patent combines multiple masking processes into a single masking step by forming the active pattern, source/drain electrodes, and data line patterns simultaneously. This is achieved by depositing a conductive metal material layer that covers the entire substrate and then performing one photolithography process to pattern all three structures at once, eliminating the need for separate masking steps for each component.
3Ease of manufacture
If conventional masking processes are used to form data lines, then the data line pattern can be created, but protruded active tails are formed that generate wavy noise and distort liquid crystal movement
Solution Approach 1:
The patent applies different etching conditions to different regions of the substrate during the single masking process. By controlling the etching parameters, the active pattern is formed with precise boundaries while the data line patterns are formed with clean edges that do not protrude. This local differentiation in etching quality prevents the formation of protruded active tails at the data line interfaces, eliminating the source of wavy noise.
4Productivity
If the number of masking processes is reduced to improve productivity, then production efficiency increases, but the manufacturing precision and control over TFT structure may deteriorate
Solution Approach 1:
The patent utilizes changes in etching parameters to achieve different patterning results from a single masking process. By adjusting etching time, power, gas flow rates, and chemical composition during the plasma etching process, the method achieves precise control over the active pattern geometry and the data line pattern geometry simultaneously. This parameter control ensures that reducing the number of masking steps does not compromise the structural precision of the TFT components.
Data Source
AI summary
A liquid crystal display device including a gate electrode and a gate line formed on a first substrate, a first insulating layer formed on the first substrate, an active pattern, an ohmic-contact layer, and a diffusion preventing layer formed on the gate electrode, a data line to cross source and drain electrodes and the gate line formed on the diffusion preventing layer to define a pixel area, a second insulating layer formed on the first substrate, a contact hole formed by removing a portion of the second insulating layer and exposing a portion of the drain electrode, a pixel electrode electrically connected with the drain electrode via the contact hole, and a second substrate attached with the first substrate in a facing manner, wherein the diffusion preventing layer comprises a metal tip protruded to the side of the source and drain electrodes.