3D Stacked Nonvolatile Memory Wiring Complexity Reduction
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Solution Overview
Problem
The complexity of wiring in three-dimensional stacked nonvolatile semiconductor memories, such as BiCS-NAND flash memory, arises due to the increased number of select gate lines on the bit line side, which complicates the connection between memory cells and drivers, especially when compared to two-dimensional structures.
Innovation Solution
The solution involves a structure where at least two or three conductive layers with specific configurations are used on both the memory cell array and the driver, allowing select gate lines on the bit line side to be shared between blocks, thereby reducing wiring complexity by decreasing the driver area and increasing the number of conductive layers, and optimizing the layout to minimize signal delay and coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of select gate lines on the bit line side is increased to accommodate the three-dimensional stacked structure, then the memory capacity is improved, but the wiring complexity increases
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure by vertically stacking multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) on the semiconductor substrate. This vertical stacking allows multiple select gate lines to share the same physical space, thereby increasing memory capacity without proportionally increasing wiring complexity on the substrate surface.
Solution Approach 2:
The patent implements a shared driver structure where a single driver can control select gate lines across multiple blocks through the stacked conductive layers. The driver serves multiple functions by providing select gate signals to both the first block and second block via the vertically stacked conductive layers, reducing the number of drivers needed and simplifying the overall wiring architecture.
2Quantity of substance
If multiple conductive layers are stacked to increase memory capacity, then the storage density is improved, but the driver area increases
Solution Approach 1:
The patent merges the driver structures for multiple blocks into a single shared driver. The driver is positioned to provide select gate signals to both the first block and second block through the stacked conductive layers, consolidating what would traditionally require separate drivers for each block into one unified structure, thereby reducing the overall driver area.
Solution Approach 2:
By utilizing the vertical dimension through stacked conductive layers, the patent enables a single driver to control multiple blocks in different lateral positions. The select gate lines extend vertically through the stacked layers, allowing one driver to serve multiple blocks without requiring proportional increases in driver area.
3Shape
If select gate lines are disposed in one block according to the BiCS memory structure, then the three-dimensional stacking is achieved, but the wiring connection complexity increases
Solution Approach 1:
The patent achieves three-dimensional stacking by vertically arranging multiple conductive layers (first, second, and third conductive layers) on the semiconductor substrate. This vertical arrangement allows select gate lines to be disposed in a stacked configuration, maintaining the BiCS memory structure while managing wiring connections through the vertical dimension rather than lateral expansion.
Solution Approach 2:
The stacked conductive layers act as intermediaries that facilitate the connection between the driver and multiple blocks. The conductive layers transmit select gate signals from the driver through the vertical stack to the appropriate blocks, simplifying the wiring connection architecture by providing a structured pathway for signal distribution.
Data Source
AI summary
A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that of the at least two conductive layers in the first and second blocks are disposed on the driver, and select gate lines in the first and second blocks are connected to the driver through the at least two conductive layers on the driver.