3D Memory Select Transistors With Uniform Gate Dielectric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In 3D memory devices, variations in the fabrication process lead to inconsistent threshold voltages and on-currents in select transistors, affecting memory cell operations such as erase, program, and read, due to leakage currents caused by non-uniformities in gate dielectric thickness and other layers.
Innovation Solution
Forming select transistors with a uniformly thick gate dielectric and a conductive floating gate to reduce leakage currents, ensuring uniform threshold voltages and on-currents, and achieving a steep subthreshold slope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for select transistors in 3D memory, then manufacturing complexity is reduced, but threshold voltage consistency and on-current uniformity deteriorate due to process variations and gate dielectric thickness non-uniformities
Solution Approach 1:
The patent applies local quality by forming a gate dielectric layer with uniformly controlled thickness specifically in the select transistor region, distinct from other areas. This localized precision in gate dielectric formation ensures consistent threshold voltages and on-currents in select transistors without requiring uniform enhancement across the entire device structure, thereby improving manufacturing precision without proportionally increasing overall fabrication complexity.
2Reliability
If gate dielectric thickness is increased to reduce leakage currents, then reliability improves, but manufacturing precision deteriorates due to difficulty in achieving uniform thickness control
Solution Approach 1:
The patent employs parameter changes by optimizing the thickness of the gate dielectric layer to a specific range that balances leakage current reduction with manufacturability. By carefully selecting and controlling the gate dielectric thickness parameter, the invention achieves reliable leakage current suppression while maintaining feasible manufacturing precision through advanced deposition techniques that can achieve uniform thickness at the optimized parameter value.
3Reliability
If select transistor threshold voltage is tightened to improve memory cell operations, then memory operation reliability improves, but device complexity increases due to additional process steps required for precise threshold voltage control
Solution Approach 1:
The patent applies preliminary action by establishing precise threshold voltage characteristics during the fabrication process itself, rather than requiring subsequent adjustment steps. By controlling gate dielectric thickness and transistor structure parameters in advance during manufacturing, the select transistors achieve tight threshold voltage distribution that ensures consistent memory cell operations (erase, program, read) without needing additional post-fabrication process steps, thus improving reliability without significantly increasing device complexity.
Data Source
AI summary
Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.