Metal Floating Gate 3D NAND Fabrication
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Solution Overview
Problem
Conventional three-dimensional NAND memories face issues with slower erase times, less desirable data retention, and charge spreading due to the use of silicon nitride charge storage dielectric layers, which can be improved by employing low work function conducting floating gates.
Innovation Solution
The method involves forming metal floating gates, such as tungsten, in recesses within the three-dimensional NAND structure using a sequential deposition-etch sequence, allowing for a different fabrication order that avoids high temperature annealing, which typically degrades tunnel dielectric quality and channel crystallization, and enabling deeper backside recesses for improved charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If silicon nitride charge storage dielectric layers are used in conventional three-dimensional NAND memories, then charge storage capacity is achieved, but program/erase speed is slow and data retention is poor
Solution Approach 1:
The patent changes the material parameter from silicon nitride dielectric to metal floating gate material, fundamentally altering the charge storage mechanism. This parameter change enables faster program/erase speeds while improving data retention characteristics through the metal's superior electrical conductivity and charge trapping capabilities.
Solution Approach 2:
The invention employs a composite structure combining metal floating gate material with tunnel dielectric and blocking dielectric layers. This composite approach integrates the high conductivity of metal with the insulating properties of dielectric materials, achieving both fast charge injection and reliable charge retention.
2Stability of the object's composition
If high temperature annealing is performed during fabrication, then material crystallization is improved, but tunnel dielectric quality degrades
Solution Approach 1:
The patent performs channel crystallization and tunnel dielectric formation in a predetermined sequence before metal floating gate deposition. By completing the tunnel dielectric formation first at lower temperatures, then performing channel crystallization afterward, the process avoids exposing the tunnel dielectric to high temperatures that would degrade its quality.
Solution Approach 2:
The invention inverts the conventional fabrication sequence by forming the metal floating gate structure before completing the channel crystallization process. This reversal allows channel treatment to occur after the temperature-sensitive tunnel dielectric is already in place, protecting it from thermal damage.
3Ease of manufacture
If conventional fabrication processes are used, then manufacturing is straightforward, but thermal budget constraints limit device performance
Solution Approach 1:
The patent segments the fabrication process into distinct temperature stages: low-temperature tunnel dielectric formation, intermediate-temperature metal floating gate deposition, and subsequent channel crystallization. This segmentation allows each step to be optimized for its specific temperature range, improving overall device performance without requiring a single high-temperature process.
Data Source
AI summary
A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.