Self-Aligned MOS Structure with Local Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device manufacturing techniques face limitations in reducing cell size below 70 nanometers, particularly in MOS transistor devices, due to practical limits of processes and equipment used.
Innovation Solution
A method involving a semiconductor substrate with a dielectric layer, polysilicon gate layer, and capping layer is used to form a self-aligned contact structure, including patterning, sidewall spacer formation, dopant implantation, and silicide layer formation, allowing for smaller transistor cell sizes without substantial modifications to conventional processes or equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor manufacturing processes are used, then manufacturing simplicity is maintained, but device feature size cannot be reduced below 70 nanometers
Solution Approach 1:
The fabrication process is divided into distinct stages: forming gate and interconnect structures, depositing sidewall spacers, selectively removing spacers from interconnect structures, forming contact holes, and creating silicide layers. This segmentation allows each step to be optimized independently while maintaining overall process compatibility with conventional manufacturing
Solution Approach 2:
Sidewall spacers are formed on both gate and interconnect structures before contact hole formation. This preliminary action establishes precise alignment references that enable sub-70nm feature sizing in subsequent processing steps without requiring new equipment
2Productivity
If device size is reduced to increase circuit density, then productivity increases, but manufacturing precision requirements become more difficult to achieve
Solution Approach 1:
The sidewall spacers serve a dual function: they act as structural support during processing and automatically define the contact hole alignment and dimensions. This self-aligning mechanism eliminates the need for separate alignment steps, enabling precise feature size control as devices scale to higher densities
Solution Approach 2:
The method changes the critical parameter from direct photolithographic patterning to spacer thickness control. By controlling the deposited spacer layer thickness rather than relying solely on lithographic resolution, the process achieves precise sub-70nm feature dimensions compatible with high circuit density requirements
3Manufacturing precision
If self-aligned contact structures are formed using sidewall spacers, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The sidewall spacers perform multiple functions simultaneously: they provide structural support, define contact hole alignment, control contact dimensions, and serve as etch masks. This multi-functionality achieves precise contact alignment without requiring separate alignment structures, thereby managing device complexity
Solution Approach 2:
The gate and interconnect structures are formed in the same polysilicon layer using a single patterning step, and the sidewall spacers are formed on both structures simultaneously. This merging of formation steps reduces the number of separate structures needed, achieving precision while controlling overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the fabrication of smaller transistor cell sizes, increasing device yields and allowing for higher circuit density, compatible with conventional technology, and achieving cell sizes less than three times the minimum transistor gate dimension.
Implementation Method 1
The method diffuses the dopant impurity from the contact polysilicon into the contact region in the substrate to form a diffused junction region
Implementation Method 2
forming a silicide layer overlying the gate structure and surface of the contact polysilicon
Data Source
AI summary
An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers.