3D Memory Source-Side Select Layout for Isolated Source Layers
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently isolating and patterning source layers and select gate electrodes, leading to limitations in memory density and operational efficiency.
Innovation Solution
A three-dimensional memory device design featuring alternating stacks of insulating and conductive layers with vertically extending memory openings and fill structures, where source layers are laterally spaced and electrically isolated, and source-side select gate electrodes are formed between the source layers and word lines with dielectric isolation, enabling precise control and increased memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If source layers are laterally spaced apart and electrically isolated, then memory density is improved, but device complexity increases
Solution Approach 1:
The source region is divided into multiple laterally spaced source layers (first source layer, second source layer, third source layer) that are electrically isolated from each other. This segmentation allows independent control and connection to different bit line groups, increasing memory density while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent transitions from a two-dimensional planar source structure to a three-dimensional stacked architecture where source layers are arranged vertically and laterally at different heights. This dimensional change enables increased storage capacity within the same footprint by utilizing the vertical dimension for additional isolated source layers.
2Productivity
If source-side select gate electrodes are separated and isolated by dielectric structures, then operational efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The source-side select gate electrodes are segmented into separate structures (first source-side select gate electrode, second source-side select gate electrode) positioned at different vertical levels. These segmented electrodes are electrically isolated by dielectric structures, enabling independent operation and improved efficiency while the dielectric isolation provides clear manufacturing boundaries.
Solution Approach 2:
Dielectric structures serve as intermediary elements that electrically isolate the separated source-side select gate electrodes from each other. These intermediary dielectric layers provide both electrical isolation and physical spacing, facilitating manufacturing by defining clear separation boundaries between conductive elements.
3Quantity of substance
If alternating stacks of insulating and conductive layers are used, then memory density is enhanced, but ease of manufacture decreases
Solution Approach 1:
The patent employs periodic alternating stacks of insulating layers and conductive layers formed through repeated deposition cycles. This periodic structure creates a regular, repeating pattern that, while complex, follows a systematic manufacturing rhythm that can be automated through sequential deposition processes, making the complex structure more manufacturable.
Solution Approach 2:
The memory device utilizes composite layered structures combining different insulating materials and conductive materials in alternating sequences. These composite material stacks provide both the required electrical isolation and conductivity functions while the layered composite architecture allows for modular fabrication through sequential material deposition.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.