3D Non-Volatile Memory Device Selection Line Merging

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Solution Overview

Problem

Conventional three-dimensional non-volatile memory devices have complex operating methods due to the need for separate voltage control of source and drain selection lines, and their stacked structure can lean, limiting storage capacity and integration.

Innovation Solution

A three-dimensional non-volatile memory device with common source and drain selection lines that control multiple strings, reducing the number of lines and preventing the stacked structure from leaning, allowing for simpler operation and increased storage capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate source and drain selection line layers are stacked to control each string individually, then precise voltage control for memory operation is achieved, but device complexity and stacked structure height increase

Engineering Contradiction:
Improvevoltage control precisionVSAvoidselection line structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges separate source and drain selection line layers into a unified selection line structure that controls multiple strings simultaneously. This consolidation reduces the number of stacked layers and simplifies the overall device architecture while maintaining effective voltage control for memory operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The selection line structure is designed to serve multiple functions: it controls both source and drain selection transistors across multiple strings (2N strings) through a single unified layer, rather than requiring separate dedicated layers for each control function. This multi-functional design reduces complexity while preserving operational precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If stacked structure height is increased to accommodate more selection line layers for higher storage capacity, then storage capacity increases, but structural stability decreases and leaning occurs

Engineering Contradiction:
Improvestorage capacityVSAvoidstacked structure stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

By merging selection line layers into a consolidated structure, the patent reduces the total height of the stacked architecture. This consolidation maintains storage capacity through efficient multi-string control while reducing structural height to prevent leaning and improve stability.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If more selection line layers are added to control additional strings for increased storage capacity, then storage capacity increases, but operating method complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoidoperating method simplicity
Core Design Contradiction:
Quantity of substanceVSEase of operation

Solution Approach 1:

The unified selection line structure is designed to control multiple strings (2N strings) simultaneously through a single layer, enabling increased storage capacity without proportionally increasing operational complexity. The structure allows for systematic voltage control across multiple strings using a simplified addressing scheme.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8743612B2Three-dimensional non-volatile memory device
Publication Date: 2014.06.03 SK HYNIX INC
  • US8743612B2 patent drawing
  • US8743612B2 patent drawing
  • US8743612B2 patent drawing

AI summary

A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N−1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string.